F72820
OVER-CURRENT TRIP:
VDS > VSET
I D x R DS(ON) > I OCSET x R OCSET
V PHASE = V
VDS
IN -
V OCSET = V
VSET
IN -
R OCSET
OCSET
VIN = 5V
IOCSET
40uA
iD
VSET
BOOT
UGATE
PHASE
LGATE
VDS
Q1
Q2
OC
VOUT
Figure 6
6.5 Under-voltage Protection
Pins FB are monitored during converter operation by under-voltage (UV) comparators. If the FB voltage drops below
0.5V, a fault signal is generated. The internal fault logic shut down regulator simultaneously when the fault signal
triggers a restart. At time t0, VOUT has dropped below 0.5V of the nominal output voltage. Output is quickly shut
down and the internal soft-start function begins producing soft-start ramps. The delay interval, t0 to 3*tss, seen by
the output is equivalent to three soft-start cycles. After a short delay interval of 10.5ms, the fourth internal soft-start
cycle initiates a normal soft-start ramp of the output, at time 3*tss. Both outputs are brought back into regulation by
time 4*tss, as long as the UV event has cleared. When the cause of the UV still been present after the delay interval.
A fault signal could then be generated and the outputs once again shutdown.
3V
VOUT
1.5V
0V
t0
tss
2tss
3tss
4tss TIME
Delay interval
Figure 7
F72820
-6-
Jul 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
