F71872
capability.
I/OD12t
- TTL level bi-directional pin, Open-drain outpu with 12 mA sink capability.
I/OD12ts5V
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability,
5V tolerance.
I/O12ts5V
- TTL level bi-directional pin and schmitt trigger with 12 mA sink capability, 5V tolerance.
- TTL level bi-directional pin, Open-drain outpu with 16 mA sink capability, 5V tolerance.
I/OD16t,5V
I/O8t-u47,5V - TTL level bi-directional pin with 8 mA sink capability, pull-up 47k ohms, 5V tolerance.
O12
- Output pin with 12 mA source-sink capability.
- Output pin(Analog).
AOUT
OD12
- Open-drain output pin with 12 mA sink capability.
OD16-u10,5V - Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.
OD24
INt5V
INts
- Open-drain output pin with 24 mA sink capability.
- TTL level input pin,5V tolerance.
- TTL level input pin and schmitt trigger.
- TTL level input pin and schmitt trigger, 5V tolerance.
- Input pin(Analog).
INts5V
AIN
P
- Power.
5.1 Power Pin
Pin No.
Pin Name
VCC
VSB
Type
P
P
Description
4,35,99
67
69
Power supply voltage input with 3.3V
Stand-by power supply voltage input 3.3V
Battery voltage input
VBAT
P
86
AGND(D-)
GND
P
P
Analog GND
Digital GND
15,50,74, 117
5.2 LPC Interface
Pin No.
37
38
39
40
Pin Name
LRESET#
LDRQ#
SERIRQ
LFRAM#
Type
INts
O12
I/O12t
INts
PWR
VCC
VCC
VCC
VCC
Description
Reset signal. It can connect to PCIRST# signal on the host.
Encoded DMA Request signal.
Serial IRQ input/Output.
Indicates start of a new cycle or termination of a broken
cycle.
41-44
LAD[3:0]
I/O12t
VCC
These signal lines communicate address, control, and data
information over the LPC bus between a host and a
peripheral.
47
49
PCICLK
CLKIN
INts
INts
VCC
VCC
33MHz PCI clock input.
System clock input. According to the input frequency
24/48MHz.
7
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
