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F71862FG 参数 Datasheet PDF下载

F71862FG图片预览
型号: F71862FG
PDF下载: 下载PDF文件 查看货源
内容描述: 超级硬件监控+ LPC I / O [Super Hardware Monitor + LPC I/O]
分类和应用: 监控PC
文件页数/大小: 110 页 / 837 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71862  
8.4UART 2 Registers (CR02)  
8.4.1  
UART 2 Device Enable Register Index 30h  
Bit Name R/W Default  
UART 2 Configuration Registers  
Description  
7-1 Reserved  
UR2_EN  
-
-
Reserved  
0
R/W  
1
0: disable UART 2.  
1: enable UART 2.  
Base Address High Register Index 60h  
Bit Name R/W Default  
Description  
7-0 BASE_ADDR_HI  
R/W  
02h The MSB of UART 2 base address.  
Base Address Low Register Index 61h  
Bit Name R/W Default  
Description  
7-0 BASE_ADDR_LO  
R/W  
F8h The LSB of UART 2 base address.  
IRQ Channel Select Register Index 70h  
Bit Name R/W Default  
Description  
7-4 Reserved  
-
-
Reserved.  
Select the IRQ channel for UART 2.  
3-0 SELUR2IRQ  
R/W  
3h  
RS485 Enable Register Index F0h  
Bit Name R/W Default  
Description  
7-5 Reserved  
-
-
Reserved.  
4
3
2
RS485_EN  
RXW4C_IR  
TXW4C_IR  
R/W  
0
0: RS232 driver.  
1: RS485 driver. Auto drive RTS# low when transmitting data.  
R/W  
R/W  
-
0
0
-
0: No reception delay when SIR is changed form TX to RX.  
1: Reception delays 4 characters time when SIR is changed form TX to RX.  
0: No transmission delay when SIR is changed form RX to TX.  
1: Transmission delays 4 characters time when SIR is changed form RX to TX.  
1-0 Reserved  
Reserved.  
SIR Mode Control Register Index F1h  
Bit  
Name  
R/W Default  
Description  
7
6
5
Reserved  
-
-
-
Reserved.  
Reserved.  
Reserved.  
Reserved  
Reserved  
-
-
-
4-3 IRMODE  
R/W  
00  
00: disable IR function.  
01: disable IR function.  
10: IrDA function, active pulse is 1.6uS.  
11: IrDA function, active pulse is 3/16 bit time.  
80  
July, 2008  
V.28P  
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