F71869A
5.9 Intel Cougar Point Timing (CPT)
The F71869A supports Intel Cougar Point Chipset timing for Sandy Bridge. There are 4 pins
for CPT control: SUS_WARN#, SUS_ACK#, SLP_SUS# and DPWROK.
For entering Intel Deep Sleep Well (DSW) state, the PCH will assert SUS_WARN# and turn off
5VDUAL. After the level of 5VDUAL is lower than 1.05V, F71869A will assert SUS_ACK# to inform
PCH it is ready for entering DSW. Finally, PCH will ramp down the internal VccSUS and assert
SLP_SUS# to F71869A. F71869A will turn off the 5VSB and 3VSB by ERP_CTRL0# and enter the
DSW state.
To exit DSW state, PCH will de-assert SLP_SUS#, turn on the SUS rail FETs and ramp up
internal 1.05V VccSUS. After the SUS rails voltages are up, RSMRST# will be desserted and the
PCH will release SUS_WARN# so that the 5VDUAL will ramp up.
Because the DSW function is controlled by F71869A instead of controlled by PCH directly,
there will be more wakeup events such as LAN, KB/Mouse, SIO RI# wake up rather than the 3
wakeup events (RTC, Power Button and GPIO27) for Intel DSW.
In order to achieve lower power consumption, F71869A provides the ERP_CTRL1# to turn off
the V3A so that the system can enter the Fintek G3’ state.
The block diagram below shows how the connection and control method for F71869A and
PCH.
47
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
