欢迎访问ic37.com |
会员登录 免费注册
发布采购

F71869A 参数 Datasheet PDF下载

F71869A图片预览
型号: F71869A
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O +硬件监控 [Super I/O + Hardware Monitor]
分类和应用: 监控
文件页数/大小: 156 页 / 1561 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
 浏览型号F71869A的Datasheet PDF文件第32页浏览型号F71869A的Datasheet PDF文件第33页浏览型号F71869A的Datasheet PDF文件第34页浏览型号F71869A的Datasheet PDF文件第35页浏览型号F71869A的Datasheet PDF文件第37页浏览型号F71869A的Datasheet PDF文件第38页浏览型号F71869A的Datasheet PDF文件第39页浏览型号F71869A的Datasheet PDF文件第40页  
F71869A  
(2). After the period of detecting fan full speed, PWM_Duty > Min. Duty, fan count is still in  
0xFFF.  
5.3 ACPI Function  
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the  
use of power in a computer. It lets computer manufacturer and user to determine the  
computer’s power usage dynamically.  
There are three ACPI states that are of primary concern to the system designer and they are  
designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this  
state. The other two are called sleep states and reflect different power consumption when  
power-down. S3 is a state that the processor is powered down but the last procedural state is  
being stored in memory which is still active. S5 is a state that memory is off and the last  
procedural state of the processor has been stored to the hard disk. Take S3 and S5 as  
comparison, since memory is fast, the computer can quickly come back to full-power state, the  
disk is slower than the memory and the computer takes longer time to come back to full-power  
state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3.  
It is anticipated that only the following state transitions may happen:  
S0S3, S0S5, S5S0, S3S0 and S3S5.  
Among them, S3S5 is illegal transition and won’t be allowed by state machine. It is  
necessary to enter S0 first in order to get to S5 from S3. As for transition S5S3 will occur only  
as an immediate state during state transition from S5S0. It isn’t allowed in the normal state  
transition.  
The below diagram described the timing, the always on and always off, keep last state could be  
set in control register. In keep last state mode, one register will keep the status of before power  
loss. If it is power on before power loss, it will remain power on when power is resumed,  
otherwise, if it is power off before power loss, it will remain power off when power is resumed.  
36  
Oct., 2011  
V0.19P  
 复制成功!