F71869A
This pin asserts low when the PCH is planning to enter the
DSW power state. It can detect 5VDUAL level with delay
setting supported.
SUS_WARN#
TIMING_1
INst,5v
I_VSB3V
54
Active high. Timing sequence 1 of power on/off sequence
pins. The external pull high resistor is required.
(Output detected by VCCOK(VDDOK) level good, ref
Figure 15 )
OD12,5v
Status Pin2 for S0#/S3#/S5# states application. (Default
function)
In S0# Æ S3P5_Gate# pin status is Tri-state.
In S3# ( S3P5_Gate # pin status is Low level.
In S5# ( S3P5_Gate # pin status is Tri-state, and can be
programmed Low level.
S3P5_Gate#
OD12
I_VSB3V
55
SLOTOCC#
GPIO04
INst,5v
CPU SLOTOCC# input.
General Purpose IO. GPIO function is selected by register
setting
OD12,5v
Status Pin1 for S0#/S3#/S5# states application. (Default
function)
S3_Gate#
OD12
In S0# ( S3_Gate# pin status is Tri-state.
In S3# ( S3_Gate# pin status is Low level.
In S5# ( S3_Gate# pin status is Tri-state.
General Purpose IO. GPIO function is selected by register
setting
I_VSB3V
56
62
GPIO05
I/OOD12st,5v
OD12,5v
Watch dog timer signal output.
WDTRST#
S0P5_Gate# for S0#/S3#/S5# states application.
In S0# (S0P5_Gate# pin status is Low-state.
In S3# (S0P5_Gate# pin status is Tri-state.
In S5# Æ S0P5_Gate# pin status is Tri-state, and can be
programmed Low-state.
S0P5_Gate#
OD24,5v
I_VSB3V
General Purpose IO. GPIO function is selected by register
setting
GPIO13
BEEP
I/OOD24st,5v
OD24,5v
Beep pin.
4.9 KBC Function
Pin No. Pin Name
Type
PWR
Description
Keyboard reset. This pin is high after system reset. Internal
pull high 3.3V with 10k ohms. (KBC P20)
Gate A20 output. This pin is high after system reset. Internal
pull high 3.3V with 10k ohms. (KBC P21)
40
41
KBRST#
GA20
OD16,5v,u10k
3VCC
OD16,5v,u10k
3VCC
69
70
71
72
KDATA
KCLK
I/OD16st,5V I_VSB3V Keyboard Data.
I/OD16st,5V I_VSB3V Keyboard Clock.
I/OD16st,5V I_VSB3V PS2 Mouse Data.
I/OD16st,5V I_VSB3V PS2 Mouse Clock.
MDATA
MCLK
21
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
