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F71869AD 参数 Datasheet PDF下载

F71869AD图片预览
型号: F71869AD
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O +硬件监控 [Super I/O + Hardware Monitor]
分类和应用: 监控
文件页数/大小: 156 页 / 1561 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71869A  
The PWROK delay timing from VDD3VOK by followed setting. The  
unit is 100 ms.  
00 : 1X  
01 : 2X  
10 : 3X  
11 : 4X  
4-3  
VDD_DELAY  
VINDB_EN  
R/W  
R/W  
11  
2
1
0
1
0
0
Enable the ATXPWGD de-bounce.  
Enable the LRESET_N de-bounce.  
Reserved  
PCIRST_DB_EN R/W  
Reserved R/W  
6.11.21 PCIRST Control Register Index F6h  
Bit  
Name  
R/W Default  
Description  
Select the KBC S3 state.  
7
S3_SEL  
R/W  
0
0
0: Enter S3 state when internal VDD3VOK signal de-asserted.  
1: Enter S3 state when S3# is low or the TS3 register is set to 1.  
0: PSON# is the inverted of S3# signal.  
1: PSON# will sink low only if the time after the last turn-off elapse at  
least 4 seconds.  
6
PSON_DEL_EN R/W  
Reserved  
5
4
3
2
1
0
-
-
Reserved  
PCIRST5_GATE R/W  
PCIRST4_GATE R/W  
PCIRST3_GATE R/W  
PCIRST2_GATE R/W  
PCIRST1_GATE R/W  
1
1
1
1
1
Write “0” to this bit will force PCIRST5# to sink low.  
Write “0” to this bit will force PCIRST4# to sink low.  
Write “0” to this bit will force PCIRST3# to sink low.  
Write “0” to this bit will force PCIRST2# to sink low.  
Write “0” to this bit will force PCIRST1# to sink low.  
6.11.22 Power Sequence Control Register Index F7h (powered by VBAT)  
Bit  
Name  
VDIMM_S3_ON R/W  
VDDA_S3_ON R/W  
VCORE_S3_ON R/W  
VLDT_S3_ON R/W  
R/W Default  
Description  
0: TIMING_1 will low during S3 state.  
1: TIMING_1 will be tri-state during S3 state.  
7
1
0
0
0: TIMING_2 will low during S3 state.  
1: TIMING_2 will be tri-state during S3 state.  
6
5
0: TIMING_3 will low during S3 state.  
1: TIMING_3 will be tri-state during S3 state.  
0: TIMING_4 will low during S3 state.  
1: TIMING_4 will be tri-state during S3 state.  
4
3
2
0
0
1
WDT_PWROK_EN R/W  
S0P5_Gate#_TRI R/W  
Set “1” to enable WDTRST# assert from PWROK pin.  
0: S0P5_Gate# will sink low in S5 state.  
1: S0P5_Gate# will be tri-state in S5 state.  
0: S3P5_Gate# will sink low in S5 state.  
1: S3P5_Gate# will be tri-state in S5 state.  
PWR_  
R/W  
1
0
1
0
S3P5_Gate#_TRI  
Reserved  
R/W  
Reserved  
6.11.23 LED VCC Mode Select Register Index F8h  
Bit Name R/W Default  
Description  
139  
Oct., 2011  
V0.19P  
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