Feature Integration Technology Inc.
Fintek
F15353
*3 Transmit ACK=0 to F15353 from the master device during reading
18
1
9
SCL
SDA
R/W
S
T
A
R
T
S
T
O
P
A
CK
A
CK
*1
0
1
1
0
1
0
*1
LSB
MSB
LSB
MSB
Command
Status Data
IO Mode Switching
Figure 14: INT1 register_1 access and INT1 register_2 (frequency duty data) access
*1 0: Status Register_1 selected, 1: Status Register_2 selected
*2 Set NO_ACK to 1 during reading
6.9.5 Clock Adjustment Register Access
18
1
9
SCL
R/W
S
T
A
R
T
S
T
O
P
A
C
K
A
0
1
1
0
1 1 0
SD
C
K
*1
LSB
MSB
LSB
MSB
Command
Clock Adjustment Data
IO Mode Switching
Figure 15: Clock adjustment register access
*1 Set NO_ACK to 1 during reading,
V0.12P
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FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
