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FWLF1524P2V57 参数 Datasheet PDF下载

FWLF1524P2V57图片预览
型号: FWLF1524P2V57
PDF下载: 下载PDF文件 查看货源
内容描述: 4个千兆符合RoHS CWDM SFP收发器 [4 Gigabit RoHS Compliant CWDM SFP Transceiver]
分类和应用: 光纤
文件页数/大小: 11 页 / 412 K
品牌: FINISAR [ FINISAR CORPORATION. ]
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FWLF1524P2Vxx SFP Product Specification – October 2006  
F i n i s a r  
I.  
Pin Descriptions  
Pin  
Symbol  
Name/Description  
Ref.  
1
2
3
4
5
6
7
VEET  
TFAULT  
TDIS  
Transmitter Ground (Common with Receiver Ground)  
Transmitter Fault. Not supported.  
Transmitter Disable. Laser output disabled on high or open.  
1
2
3
3
3
4
MOD_DEF(2) Module Definition 2. Data line for Serial ID.  
MOD_DEF(1) Module Definition 1. Clock line for Serial ID.  
MOD_DEF(0) Module Definition 0. Grounded within the module.  
Rate Select  
Open or Low =  
1.063 Gb/s or 2.125 Gb/s Fibre Channel, 1.25 Gb/s  
Gigabit Ethernet (Low Bandwidth)  
High =  
2.125 or 4.25 Gb/s Fibre Channel (High Bandwidth)  
8
9
LOS  
VEER  
VEER  
VEER  
RD-  
RD+  
VEER  
VCCR  
VCCT  
VEET  
TD+  
TD-  
Loss of Signal indication. Logic 0 indicates normal operation.  
Receiver Ground (Common with Transmitter Ground)  
Receiver Ground (Common with Transmitter Ground)  
Receiver Ground (Common with Transmitter Ground)  
Receiver Inverted DATA out. AC Coupled  
Receiver Non-inverted DATA out. AC Coupled  
Receiver Ground (Common with Transmitter Ground)  
Receiver Power Supply  
5
1
1
1
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
1
1
1
Transmitter Power Supply  
Transmitter Ground (Common with Receiver Ground)  
Transmitter Non-Inverted DATA in. AC Coupled.  
Transmitter Inverted DATA in. AC Coupled.  
Transmitter Ground (Common with Receiver Ground)  
VEET  
Notes:  
1. Circuit ground is internally isolated from chassis ground.  
2. Laser output disabled on TDIS >2.0V or open, enabled on TDIS <0.8V.  
3. Should be pulled up with 4.7k - 10 kohms on host board to a voltage between 2.0V and 3.6V.  
MOD_DEF(0) pulls line low to indicate module is plugged in.  
4. Specific information when selecting line rate: Rate selection is done in accordance with SFF  
Committee SFF-8079 Draft, Rev.1.6, Table 3. Note that rate select can also be set through 2-wire bus  
in accordance with SFF-84726 at Bit 3, Byte 110, Address A2h (note: writing ‘1’ selects full bandwidth  
operation). Rate select is the logic OR of the input state of Rate Select Pin and 2-wire bus. Non Rate  
Selectable version can operate at 1x, 2x, 4x Fibre Channel independent of rate select pin setting.  
5. LOS is open collector output. Should be pulled up with 4.7k – 10 kohms on host board to a voltage  
between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.  
VeeT  
TD-  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VeeT  
1
2
TXFault  
TD+  
3
TX Disable  
MOD-DEF(2)  
MOD-DEF(1)  
MOD-DEF(0)  
Rate Select  
LOS  
VeeT  
VccT  
VccR  
VeeR  
RD+  
RD-  
4
5
Towards  
Bezel  
Towards  
ASIC  
6
7
8
9
VeeR  
VeeR  
VeeR  
10  
Pinout of Connector Block on Host Board  
Ó Finisar Corporation October 31, 2006 Rev C Preliminary  
Page 2  
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