欢迎访问ic37.com |
会员登录 免费注册
发布采购

FTLX3815M324 参数 Datasheet PDF下载

FTLX3815M324图片预览
型号: FTLX3815M324
PDF下载: 下载PDF文件 查看货源
内容描述: [Multiprotocol 80Km, 10Gb/s DWDM XFP Optical Transceiver]
分类和应用:
文件页数/大小: 23 页 / 934 K
品牌: FINISAR [ FINISAR CORPORATION. ]
 浏览型号FTLX3815M324的Datasheet PDF文件第6页浏览型号FTLX3815M324的Datasheet PDF文件第7页浏览型号FTLX3815M324的Datasheet PDF文件第8页浏览型号FTLX3815M324的Datasheet PDF文件第9页浏览型号FTLX3815M324的Datasheet PDF文件第11页浏览型号FTLX3815M324的Datasheet PDF文件第12页浏览型号FTLX3815M324的Datasheet PDF文件第13页浏览型号FTLX3815M324的Datasheet PDF文件第14页  
FTLX3815M3xx DWDM XFP Product Specification Nov 2014  
F i n i s a r  
VIII. Digital Diagnostics Functions  
As defined by the XFP MSA1, Finisar XFP transceivers provide digital diagnostic  
functions via a 2-wire serial interface, which allows real-time access to the following  
operating parameters:  
Transceiver temperature  
Laser bias current  
Transmitted optical power  
Received optical power  
Transceiver supply voltage  
TEC Temperature  
It also provides a sophisticated system of alarm and warning flags, which may be used to  
alert end-users when particular operating parameters are outside of a factory-set normal  
range.  
The operating and diagnostics information is monitored and reported by a Digital  
Diagnostics Transceiver Controller (DDTC) inside the transceiver, which is accessed  
through the 2-wire serial interface. When the serial protocol is activated, the serial clock  
signal (SCL pin) is generated by the host. The positive edge clocks data into the XFP  
transceiver into those segments of its memory map that are not write-protected. The  
negative edge clocks data from the XFP transceiver. The serial data signal (SDA pin) is  
bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to  
mark the start and end of serial protocol activation. The memories are organized as a  
series of 8-bit data words that can be addressed individually or sequentially. The 2-wire  
serial interface provides sequential or random access to the 8 bit parameters, addressed  
from 000h to the maximum address of the memory.  
For more detailed information, including memory map definitions, please see the XFP  
MSA documentation1.  
Receiver Threshold Adjustment  
The FTLX3815M3xx also provide access to receiver decision threshold adjustment via 2-  
wire serial interface, in order to improve receiver OSNR performance based on specific  
link conditions. It is implemented as follows:  
Rx Threshold of XFP transceivers will be factory-set for optimized performance  
in non-FEC applications. This will be the default value during both cold start  
(power-up) and warm start (module reset).  
Rev.: A04  
Page 10 of 23  
1174161  
This document contains proprietary and confidential information to Finisar Corp. This document and the entire information  
contained herein, and any other tangible representation thereof, is not to be copied, reproduced, duplicated, distributed, or  
modified, in whole or in part, and/or used without the expressed written consent of Finisar Corp.  
Printed copy may not be the latest revision please refer to Agile for current revision