FTLX1451 Product Specification – November 2007
I. Pin Descriptions
Signal Name
Level
I/O
Management and Monitoring Ports
MDIO
Open Drain
I/O
MDC
PRTAD4
PRTAD3
PRTAD2
PRTAD1
PRTAD0
LASI
1.2 V
CMOS
1.2 V
CMOS
1.2 V
CMOS
1.2 V
CMOS
1.2 V
CMOS
1.2 V
CMOS
Open Drain
I
1
I
I
I
I
O
Pin No.
17
18
19
20
21
22
23
9
Description
Management Data I/O. Requires
external 10 - 22 kΩ pull-up to the
APS on host.
Management Data Clock Input
Port Address Input bit 4
Port Address Input bit 3
Port Address Input bit 2
Port Address Input bit 1
Port Address Input bit 0
Link Alarm Status Interrupt
Output. Open Drain Compatible
Output with 10 - 20 kΩ pull-up on
host.
Logic high = Normal Operation
Logic low = Status Flag Triggered
Reset Input.
Open Drain Compatible Input with
22 kΩ pull-up to APS internal to
transponder.
Logic high = Normal Operation
Logic low = RESET
Vendor Specific Pins.
Leave unconnected when not used.
TX ON/OFF Input.
Open Drain Compatible Input with
22 kΩ pull-up to APS internal to
transponder.
Logic high = Transmitter On
Logic low = Transmitter Off
Pulled low inside transponder
through a 1 kΩ resistor to Ground
Reserved For Future Use
Reserved For Future Use
Module XAUI Input Lane 3–
Module XAUI Input Lane 3+
Module XAUI Input Lane 2–
Module XAUI Input Lane 2+
Module XAUI Input Lane 1–
Module XAUI Input Lane 1+
Module XAUI Input Lane 0–
Module XAUI Input Lane 0+
RESET
Open Drain
I
10
Vendor
Specific
TX ON/OFF
11,15,16,24
Open Drain
I
12
MOD
DETECT
Transmit Functions
Reserved
Reserved
AC-coupled,
TX LANE 3–
Internally
TX LANE 3+
biased
differential
TX LANE 2–
XAUI
TX LANE 2+
TX LANE 1–
TX LANE 1+
TX LANE 0–
TX LANE 0+
O
I
I
I
I
I
I
I
I
I
I
14
68
67
65
64
62
61
59
58
56
55
©
Finisar Corporation – November 2007 Rev. B
Page 2
FINISAR [ FINISAR CORPORATION. ]
