FTL-1621-XX CWDM GBIC
Product Specification – February 2007
Finisar
Parameter
RX_LOS Assert Level
RX_LOS Deassert Level
RX_LOS Hysteresis
RX_LOS Assert Delay
RX_LOS Negate Delay
TX_DISABLE Assert Time
Symbol Min
--
-42
--
--
t_loss_on
t_loss_off
t_off
Typ
-39
-37
1.0
Max
-32
100
150
1000
Units
dBm
dBm
dB
µsec
µsec
µsec
µsec
µsec
TX_DISABLE Negate Time
t_on
1000
TX_DISABLE Reset Time
t_reset
10
Notes/Conditions
Measured on Finisar Eval Card
Measured on Finisar Eval Card
Measured on Finisar Eval Card
From detection of loss of signal
to assertion of RX_LOS
From detection of presence of
signal to negation of RX_LOS
Rising edge ot TX_DISABLE to
fall of output signal below 10%
of nominal
Falling edge of TX_DISABLE
to rise of output signal above
90% of nominal
TX_DISABLE HIGH before
TX_DISABLE set LOW
Table 4. Low speed signal parameters
IV. High Speed Electrical Interface
All high-speed PECL signals are AC coupled internally.
Parameter
Data Input Voltage
Data Output Voltage
Duty Cycle
PECL rise/fall
Bit Error Rate
Tx Input Impedance
Rx Output Impedance
Symbol
V
in
V
out
--
T
r
,T
f
BER
Z
in
Z
out
Min
650
370
Typ
Max
2000
2000
150
10
-12
50
Units
mV
mV
%
psec
ohm
ohm
Notes/Conditions
PECL differential peak - peak
PECL differential peak - peak
20%-80% Differential
PRBS 2
23
- 1 test data pattern
Singled ended impedance
Singled ended impedance
75
75
Table 5. High speed electrical interface
© Finisar Corporation February 2007 Rev.B
Page 4
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