MC81F4x16
8.2 Read Timing
Volt
OSC.
Stabilization
Time
VDD rising curve
32 ms
@4MHz
32 ms
POR
level
Time
Rom option
Read
POR
Start
Reset process
& Main program
Start
Figure 8-1 ROM option read timing diagram
Rom option is affected 32 mili-second (typically) after VDD cross the POR level. More precisely
saying, the 32 mili-second is the time for 1/2 counting of 1024 divided BIT with 4 MHz internal OSC.
After the ROM option is affected, system clock source is changed based on the ROM option. And then,
rest 1/2 counting is continued with changed clock source. So, hole stabilization time is variable
depend on the clock source.
Before read
ROM option
After read
ROM option
OSC Stabilization Time
Before + After
Formula
250ns x 128(BTCR) x Period x 128(BTCR) x
1024(divider)
1024(divider)
Int-RC 4MHz
Int-RC 8MHz
X-tal 12 MHz
X-tal 16 Mhz
32 ms
32 ms
64 ms
48 ms
32 ms
16 ms
32 ms
10.7 ms
8 ms
42.7 ms
40 ms
32 ms
Table 8-1 examples of OSC stabilization time
Note that ROM option is affected in OSC stabilization time. So even you change the ROM option by
ISP. It is not affected until system is reset. In other words, you must reset the system after change the
ROM option.
48
October 19, 2009 Ver.1.35
FINECHIPS [ FINECHIPS ]
