MC81F4x16
23.1 Registers
SIOCR
SERIAL I/O INTERFACE CONTROL REGISTER
00E7H
A reset clears the SIOCR register value to "00H". With this value, internal clock source and receive-
only mode are selected and the 3-bit counter is cleared. The data shift operation is disabled. The
selected data direction is MSB-first.
7
–
–
6
–
–
5
4
3
2
1
0
CSEL
R/W
DAT
R/W
SIOM
R/W
SIOP
R/W
CCLR SEDGE
R/W R/W
SIOCR
Reset value:
--00_0000b
–
bit7 – bit6
Not used for MC81F4432
0: Internal clock (P.S clock)
1: External clock (SCK)
CSEL
SIO Shift Clock Selection Bit
Data Direction Control Bit
SIO Mode Selection Bit
0: MSB-first mode
DAT
SIOM
SIOP
1: LSB-first mode
0: Receive only mode
1: Transmit/Receive mode
0: Disable shifter and clock counter
1: Enable shifter and clock counter
0: No action
SIO Shift Operation Enable Bit
CCLR
SEDGE
SIO Counter Clear and Shift Start Bit
Shift Clock Edge Selection Bit
1: Clear 3-bit counter and start shifting
0: Tx at falling edges, Rx at rising edges
1: Tx at rising edges, Rx at falling edges
SIODAT
SIO DATA REGISTER
00E8H
7
SIODAT
6
5
4
3
2
1
0
One byte register
R/W R/W
Reset value: 00H
R/W
R/W
R/W
R/W
R/W
R/W
A 8-bit data register for SIO Rx/Tx data
SIOPS
SIO PRE-SCALER REGISTER
00E9H
7
6
5
4
3
2
1
0
SIOPS
One byte register
R/W R/W
Reset value: 00H
R/W
R/W
R/W
R/W
R/W
R/W
Baud rate = (fxx/4) / (SIOPS+1)
October 19, 2009 Ver.1.35
149
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