MC81F4x16
The bit POL2, POL3 and POL4 of PWMSCR decides the polarity of duty cycle. The duty value can be
changed when the PWM outputs. However the changed duty value is output after the current period is
over. And it can be maintained the duty value at present output when changed only period value
shown as Example of PWM2. As it were, the absolute duty time is not changed in varying frequency.
Note :
When user need to change mode from the Timer2 mode to the PWM mode, the Timer2
should be stopped firstly, and then set period and duty register value. If user writes register
values and changes mode to PWM mode while Timer2 is in operation, the PWM data would
be different from expected data in the beginning.
PWM Period = [PWMPDR[1:0]T2DR+1] X Source Clock
PWM2 Duty = [PWMPDR[3:2]PWM2DR+1] X Source Clock
PWM3 Duty = [PWMPDR[5:4]PWM3DR+1] X Source Clock
PWM4 Duty = [PWMPDR[7:6]PWM4DR+1] X Source Clock
If it needed more higher frequency of PWM, it should be reduced resolution.
Note :
If the duty value and the period value are same, the PWM output is determined by the bit
POL (1: High, 0: Low). And if the duty value is set to “00H”, the PWM output is determined by
the bit POL(1: Low, 0: High). The period value must be same or more than the duty value,
and 00H cannot be used as the period value.
Source clock
PWM Period,
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
80 81 82 83 84
3FC 3FD 3FE 3FF 00 01 02 03 04
T2DR
PWM2O,
POL2=1
PWM2O,
POL2=0
Duty Cycle [(1+0CH) X 256uS = 3.33mS
Period Cycle [(1+3FFH) X 256uS = 262mS
T2SCR = 1FH
T2DR = 0FFH
PWMSCR = 30H
PWMPDR = 03H
PWM2DR = 0CH
Figure 20-2 Example of PWM2 at 8MHz
138
October 19, 2009 Ver.1.35
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