Man Portable Radar Warning Receiver
System Timing
The operation of the frequency measurement unit is as follows:
When r.f. enters the discriminator circuits, the video voltages settle after a delay
depending on the video bandwidth. The video signals are then stable and can be
digitised by the comparators and ASIC. This digitization takes a maximum of 15 ns
(ASIC worst case timing). Therefore valid raw frequency data is available 75 ns after
the leading edge of the r.f. pulse. The raw frequency data is decoded in the EPROM
look-up table which takes 55 ns.
Figure 3: System Timing Diagram
r.f.
t
rfhld
video out
t
latch
LATCH
t
lpw
Raw Data
t
dig
t
lhold
t
decode
Frequency Data Out
Data Valid
t
dechold
t
meas
Table 2: Timing
Description
time between latch edge and trailing edge of r.f
time from leading edge of r.f. and latch edge
Width of latch pulse
time to digitise video
time from latch disable and raw data invalid
time to decode raw frequency data
time to hold decoded frequency data
time from start of r.f. to valid frequency out
symbol
t
rfhld
t
latch
t
lpw
t
dig
t
lhold
t
decode
t
dechold
t
meas
min
6
60
5
max
units
ns
ns
ns
ns
ns
ns
ns
ns
15
10
55
7
130
The LATCH signal holds the digitised frequency data when it is in the logic high
state. When the LATCH signal is low, the digitising circuits are transparent and the
data buses may change state rapidly increasing current consumption, thus to reduce
this effect the latch signal should be held high and digitising initiated by a narrow
logic low pulse. In order to capture 100 ns pulses the rising edge of the LATCH signal
must occur no later than 94 ns after the start of the r.f. pulse.
Filtronic Components Ltd., Airedale House, Royal London Industrial Estate, Acorn Park, Shipley,
West Yorkshire, BD17 7SW, United Kingdom.
Tel: +44 (1274) 531602, Fax: +44 (1274) 539724, Email: sales@fcl.com
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