FPD750SOT343
Datasheet v3.0
A
BSOLUTE
M
AXIMUM
R
ATING
1
:
P
ARAMETER
Drain-Source Voltage
Gate-Source Voltage
Drain-Source Current
Gate Current
RF Input Power
2
S
YMBOL
VDS
VGS
IDS
IG
PIN
TCH
TSTG
4
PTOT
Comp.
3
T
EST
C
ONDITIONS
-3V < VGS < -0.5V
0V < VDS < +6V
For VDS < 2V
Forward or reverse current
VDS = 3.3V
Under any acceptable bias state
Non-Operating Storage
See De-Rating Note below
Under any bias conditions
2 or more Max. Limits
A
BSOLUTE
M
AXIMUM
6V
-3V
IDss
7.5mA
22dBm
175°C
-55°C to 150°C
1.1W
5dB
80%
Channel Operating Temperature
Storage Temperature
Total Power Dissipation
Gain Compression
Simultaneous Combination of Limits
Notes:
1
T
Ambient
= 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause
permanent damage to the device
2
Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3
Users should avoid exceeding 80% of 2 or more Limits simultaneously
4
Total Power Dissipation defined as: P
TOT
≡
(P
DC
+ P
IN
) – P
OUT
,
where P
DC
: DC Bias Power, P
IN
: RF Input Power, P
OUT
: RF Output Power
Total Power Dissipation to be de-rated as follows above 22°C:
P
TOT
= 1.1 - (1/Θjc) x T
PACK
where T
PACK
= source tab lead temperature above 22°C &
Θjc
= 143ºC/W
B
IASING
G
UIDELINES
:
•
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage
supply for depletion-mode devices.
For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Class A/B
bias of 25-33% offers an optimised solution for NF and OIP3.
DC IV Curves FPD750SOT89
•
•
0.30
0.25
0.20
0.15
0.10
VG=-1.50
VG=-1.25V
VG=-1.00V
VG=-0.75V
VG=-0.50V
VG=-0.25V
VG=0V
Note:
The recommended method for
measuring I
DSS
, or any particular I
DS
, is to set
the Drain-Source voltage (V
DS
) at 1.3V. This
measurement point avoids the onset of
spurious self-oscillation which would normally
distort the current measurement (this effect has
been filtered from the I-V curves presented
above). Setting the V
DS
> 1.3V will generally
cause errors in the current measurements,
even in stabilized circuits.
Drain-Source Current (A)
0.05
0.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Drain-Source Voltage (V)
2
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website:
www.filtronic.com
FILTRONIC [ FILTRONIC COMPOUND SEMICONDUCTORS ]
