FPD750DFN
Datasheet v3.0
1
ABSOLUTE MAXIMUM RATING :
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Drain-Source Current
Gate Current
SYMBOL
VDS
TEST CONDITIONS
-3V < VGS < +0V
ABSOLUTE MAXIMUM
8V
VGS
0V < VDS < +8V
-3V
IDS
For VDS > 2V
IDss
IG
Forward or reverse current
Under any acceptable bias state
Under any acceptable bias state
Non-Operating Storage
See De-Rating Note below
Under any bias conditions
2 or more Max. Limits
7.5mA
175mW
175°C
-55°C to 150°C
1.5W
2
RF Input Power
PIN
Channel Operating Temperature
Storage Temperature
TCH
TSTG
PTOT
Comp.
Total Power Dissipation
Gain Compression
5dB
3
Simultaneous Combination of Limits
Notes:
1TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause
permanent damage to the device
2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Users should avoid exceeding 80% of 2 or more Limits simultaneously
4Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT
,
where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power
Total Power Dissipation to be de-rated as follows above 22°C:
PTOT= 1.5 - (0.011W/°C) x TPACK
where TPACK= source tab lead temperature above 22°C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C carrier temperature: PTOT = 1.5W – (0.011 x (65 – 22)) = 1.03W
5The use of a filled via-hole directly beneath the exposed heatsink tab on the bottom of the package is strongly
recommended to provide for adequate thermal management. Ideally the bottom of the circuit board is affixed to a
heatsink or thermal radiator
BIASING GUIDELINES:
•
Active bias circuits provide good performance stabilisation over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate
•
•
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage
supply for depletion-mode devices.
For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at 50%
of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to
33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance.
2
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
FILTRONIC [ FILTRONIC COMPOUND SEMICONDUCTORS ]
