Instruction(FFh)
FM25Q64ꢀ
ꢀ
11.2.26ꢀModeꢀBitꢀResetꢀ(FFh)ꢀ
Forꢀ Fastꢀ Readꢀ Dual/Quadꢀ I/Oꢀ operations,ꢀ Modeꢀ Bitsꢀ (M7ꢁ0)ꢀ areꢀ implementedꢀ toꢀ furtherꢀ reduceꢀ
instructionꢀoverhead.ꢀByꢀsettingꢀtheꢀModeꢀBitsꢀ(M7ꢁ0)ꢀtoꢀ“Ax”ꢀhex,ꢀtheꢀnextꢀFastꢀReadꢀDual/Quadꢀ
I/OꢀoperationsꢀdoꢀnotꢀrequireꢀtheꢀBBh/EBhꢀinstructionꢀcodeꢀ(Seeꢀ11.2.10ꢀFastꢀReadꢀDualꢀI/Oꢀandꢀ
11.2.11ꢀ ꢀ FastꢀReadꢀQuadꢀI/Oꢀforꢀdetailꢀdescriptions).ꢀ
ꢀ
IfꢀtheꢀsystemꢀcontrollerꢀisꢀresetꢀduringꢀoperationꢀitꢀwillꢀlikelyꢀsendꢀaꢀstandardꢀSPIꢀinstruction,ꢀsuchꢀ
asꢀReadꢀIDꢀ(9Fh)ꢀorꢀFastꢀReadꢀ(0Bh),ꢀtoꢀtheꢀFM25Q32.ꢀHowever,ꢀasꢀwithꢀmostꢀSPIꢀSerialꢀFlashꢀ
memories,ꢀtheꢀFM25Q32ꢀdoesꢀnotꢀhaveꢀaꢀhardwareꢀResetꢀpin,ꢀsoꢀifꢀModeꢀbitsꢀareꢀsetꢀtoꢀ“Ax”ꢀhex,ꢀ
theꢀ FM25Q32ꢀ willꢀ notꢀ recognizeꢀ anyꢀ standardꢀ SPIꢀ instruction.ꢀ Toꢀ addressꢀ thisꢀ possibility,ꢀ itꢀ isꢀ
recommendedꢀtoꢀissueꢀaꢀModeꢀBitꢀResetꢀinstructionꢀ“FFh”ꢀasꢀtheꢀfirstꢀinstructionꢀafterꢀaꢀsystemꢀ
Reset.ꢀDoingꢀsoꢀwillꢀreleaseꢀtheꢀmodeꢀBitsꢀforꢀtheꢀ“Ax”ꢀhexꢀstateꢀandꢀallowꢀStandardꢀSPIꢀinstructionꢀ
toꢀbeꢀrecognized.ꢀTheꢀModeꢀBitsꢀResetꢀinstructionꢀisꢀshownꢀinꢀfigureꢀ26.ꢀ
ꢀ
ꢀ
/CS
Mode
Mode
3
0
0
1
2
3
4
5
6
7
Mode
Mode
3
0
CLK
0
IO
DontꢀCare
’
1
IO
DontꢀCare
’
2
IO
DontꢀCare
’
3
IO
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Figureꢀ26.ꢀModeꢀBitsꢀResetꢀforꢀFastꢀReadꢀDual/QuadꢀI/Oꢀ
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preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ
44ꢀ
FIDELIX [ FIDELIX ]
