FM25Q64ꢀ
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11.2.20ꢀEraseꢀ/ꢀProgramꢀSuspendꢀ(75h)ꢀ
TheꢀErase/ProgramꢀSuspendꢀinstructionꢀ“75h”,ꢀallowsꢀtheꢀsystemꢀtoꢀinterruptꢀaꢀSectorꢀorꢀBlockꢀ ꢀ
EraseꢀoperationꢀorꢀaꢀPageꢀProgramꢀoperationꢀandꢀthenꢀreadꢀfromꢀorꢀprogram/eraseꢀdataꢀto,ꢀanyꢀ
otherꢀsectorsꢀorꢀblocks.ꢀTheꢀErase/ProgramꢀSuspendꢀinstructionꢀsequenceꢀisꢀshownꢀinꢀfigureꢀ20.ꢀ ꢀ
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TheꢀWriteꢀStatusꢀRegisterꢀinstructionꢀ(01h)ꢀandꢀEraseꢀinstructionsꢀ(20h,ꢀ52h,ꢀD8h,ꢀC7h,ꢀ60h,ꢀ44h)ꢀ
areꢀnotꢀallowedꢀduringꢀEraseꢀSuspend.ꢀEraseꢀSuspendꢀisꢀvalidꢀonlyꢀduringꢀtheꢀSectorꢀorꢀBlockꢀ
eraseꢀ operation.ꢀ Ifꢀ writtenꢀ duringꢀ theꢀ Chipꢀ Eraseꢀ operation,ꢀ theꢀ Eraseꢀ Suspendꢀ instructionꢀ isꢀ ꢀ
ignored.ꢀTheꢀWriteꢀStatusꢀRegisterꢀinstructionꢀ(01h)ꢀandꢀProgramꢀinstructionsꢀ(02h,ꢀ32h,ꢀ42h)ꢀ ꢀ areꢀ ꢀ
notꢀallowedꢀduringꢀProgramꢀSuspend.ꢀProgramꢀSuspendꢀisꢀvalidꢀonlyꢀduringꢀtheꢀPageꢀProgramꢀorꢀ
QuadꢀPageꢀProgramꢀoperation.ꢀ ꢀ
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TheꢀErase/ProgramꢀSuspendꢀinstructionꢀ“75h”ꢀwillꢀbeꢀacceptedꢀbyꢀtheꢀdeviceꢀonlyꢀifꢀtheꢀSUSꢀbitꢀinꢀ
theꢀStatusꢀRegisterꢀequalsꢀtoꢀ0ꢀandꢀtheꢀBUSYꢀbitꢀequalsꢀtoꢀ1ꢀwhileꢀaꢀSectorꢀorꢀBlockꢀEraseꢀorꢀaꢀ ꢀ
PageꢀProgramꢀoperationꢀisꢀonꢁgoing.ꢀIfꢀtheꢀSUSꢀbitꢀequalsꢀtoꢀ1ꢀorꢀtheꢀBUSYꢀbitꢀequalsꢀtoꢀ0,ꢀtheꢀ ꢀ
Suspendꢀ instructionꢀ willꢀ beꢀ ignoredꢀ byꢀ theꢀ device.ꢀ Aꢀ maximumꢀ ofꢀ timeꢀ ofꢀ “tSUS”ꢀ (Seeꢀ ACꢀ
Characteristics)ꢀisꢀrequiredꢀtoꢀsuspendꢀtheꢀeraseꢀorꢀprogramꢀoperation.ꢀTheꢀBUSYꢀbitꢀinꢀtheꢀStatusꢀ
Registerꢀwillꢀbeꢀclearedꢀfromꢀ1ꢀtoꢀ0ꢀwithinꢀ“tSUS”ꢀandꢀtheꢀSUSꢀbitꢀinꢀtheꢀStatusꢀRegisterꢀwillꢀbeꢀ ꢀ
setꢀ fromꢀ 0ꢀ toꢀ 1ꢀ immediatelyꢀ afterꢀ Erase/Programꢀ Suspend.ꢀ Forꢀ aꢀ previouslyꢀ resumedꢀ
Erase/Programꢀoperation,ꢀitꢀisꢀalsoꢀrequiredꢀthatꢀtheꢀSuspendꢀinstructionꢀ“75h”ꢀisꢀnotꢀissuedꢀearlierꢀ
thanꢀaꢀminimumꢀofꢀtimeꢀofꢀ“tSUS”ꢀfollowingꢀtheꢀprecedingꢀResumeꢀinstructionꢀ“7Ah”.ꢀ ꢀ
ꢀ
UnexpectedꢀpowerꢀoffꢀduringꢀtheꢀErase/Programꢀsuspendꢀstateꢀwillꢀresetꢀtheꢀdeviceꢀandꢀ ꢀ releaseꢀ ꢀ
theꢀsuspendꢀstate.ꢀSUSꢀbitꢀinꢀtheꢀStatusꢀRegisterꢀwillꢀalsoꢀresetꢀtoꢀ0.ꢀTheꢀdataꢀwithinꢀtheꢀpage,ꢀ ꢀ
sectorꢀorꢀblockꢀthatꢀwasꢀbeingꢀsuspendedꢀmayꢀbecomeꢀcorrupted.ꢀItꢀisꢀrecommendedꢀforꢀtheꢀuserꢀ
toꢀ implementꢀ systemꢀ designꢀ techniquesꢀ againstꢀ theꢀ accidentalꢀ powerꢀ interruptionꢀ andꢀ preserveꢀ ꢀ
dataꢀ ꢀ integrityꢀ ꢀ duringꢀerase/programꢀsuspendꢀstate.ꢀ
ꢀ
/CS
tSUS
Modeꢀ3
Modeꢀ0
Modeꢀ3
Modeꢀ0
0
1
2
3
4
5
6
7
CLK
Instructionꢀ(75h)
DI
HighꢀImpedance
DO
AcceptꢀReadꢀorꢀProgramꢀ
Instruction
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Figureꢀ20.ꢀEraseꢀSuspendꢀinstructionꢀSequenceꢀ
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preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ
36ꢀ
FIDELIX [ FIDELIX ]
