FM25Q64ꢀ
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11.2.18ꢀ64KBꢀBlockꢀEraseꢀ(D8h)ꢀ
TheꢀBlockꢀEraseꢀinstructionꢀsetsꢀallꢀmemoryꢀwithinꢀaꢀspecifiedꢀblockꢀ(64kꢁbytes)ꢀtoꢀtheꢀerasedꢀstateꢀ
ofꢀallꢀ1sꢀ(FFh).ꢀAꢀWriteꢀEnableꢀinstructionꢀmustꢀbeꢀexecutedꢀbeforeꢀtheꢀdeviceꢀwillꢀacceptꢀtheꢀBlockꢀ
EraseꢀInstructionꢀ(StatusꢀRegisterꢀbitꢀWELꢀmustꢀequalꢀ1).ꢀTheꢀinstructionꢀisꢀinitiatedꢀbyꢀdrivingꢀtheꢀ
/CSꢀpinꢀlowꢀandꢀshiftingꢀtheꢀinstructionꢀcodeꢀ“D8h”ꢀfollowedꢀaꢀ24ꢁbitꢀblockꢀaddressꢀ(A23ꢁA0).ꢀTheꢀ
BlockꢀEraseꢀinstructionꢀsequenceꢀisꢀshownꢀinꢀfigureꢀ18.ꢀ
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Theꢀ/CSꢀpinꢀmustꢀbeꢀdrivenꢀhighꢀafterꢀtheꢀeighthꢀbitꢀofꢀtheꢀlastꢀbyteꢀhasꢀbeenꢀlatched.ꢀIfꢀthisꢀisꢀnotꢀ
doneꢀtheꢀBlockꢀEraseꢀinstructionꢀwillꢀnotꢀbeꢀexecuted.ꢀAfterꢀ/CSꢀisꢀdrivenꢀhigh,ꢀtheꢀselfꢁtimedꢀBlockꢀ
EraseꢀinstructionꢀwillꢀcommenceꢀforꢀaꢀtimeꢀdurationꢀofꢀtBE1ꢀ(SeeꢀACꢀCharacteristics).ꢀWhileꢀtheꢀ
BlockꢀEraseꢀcycleꢀisꢀinꢀprogress,ꢀtheꢀReadꢀStatusꢀRegisterꢀinstructionꢀmayꢀstillꢀbeꢀaccessedꢀforꢀ
checkingꢀ theꢀ statusꢀ ofꢀ theꢀ BUSYꢀ bit.ꢀ Theꢀ BUSYꢀ bitꢀ isꢀ aꢀ 1ꢀ duringꢀ theꢀ Blockꢀ Eraseꢀ cycleꢀ andꢀ
becomesꢀaꢀ0ꢀwhenꢀtheꢀcycleꢀisꢀfinishedꢀandꢀtheꢀdeviceꢀisꢀreadyꢀtoꢀacceptꢀotherꢀinstructionsꢀagain.ꢀ
AfterꢀtheꢀBlockꢀEraseꢀcycleꢀhasꢀfinishedꢀtheꢀWriteꢀEnableꢀLatchꢀ(WEL)ꢀbitꢀinꢀtheꢀStatusꢀRegisterꢀisꢀ
clearedꢀtoꢀ0.ꢀTheꢀBlockꢀEraseꢀinstructionꢀwillꢀnotꢀbeꢀexecutedꢀifꢀtheꢀaddressedꢀpageꢀisꢀprotectedꢀbyꢀ
theꢀ Blockꢀ Protectꢀ (SEC,ꢀ TB,ꢀ BP2,ꢀ BP1,ꢀ andꢀ BP0)ꢀ bitsꢀ (seeꢀ Statusꢀ Registerꢀ Memoryꢀ Protectionꢀ
table).ꢀ
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/CS
Modeꢀ3
Modeꢀ0
Modeꢀ3
Modeꢀ0
0
1
2
3
4
5
6
7
8
9
29 30 31
CLK
Instruction
(D8h)
24ꢁbitꢀAddress
2
1
0
DI
DO
*
23 22
*
HighꢀImpedance
=ꢀMSB
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Figureꢀ18.ꢀ64KBꢀBlockꢀEraseꢀInstructionꢀSequenceꢀDiagramꢀ
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preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ
34ꢀ
FIDELIX [ FIDELIX ]
