FM25Q64ꢀ
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11.2.17ꢀ32KBꢀBlockꢀEraseꢀ(52h)ꢀ
TheꢀBlockꢀEraseꢀinstructionꢀsetsꢀallꢀmemoryꢀwithinꢀaꢀspecifiedꢀblockꢀ(32kꢁbytes)ꢀtoꢀtheꢀerasedꢀstateꢀ
ofꢀallꢀ1sꢀ(FFh).ꢀAꢀWriteꢀEnableꢀinstructionꢀmustꢀbeꢀexecutedꢀbeforeꢀtheꢀdeviceꢀwillꢀacceptꢀtheꢀBlockꢀ
EraseꢀInstructionꢀ(StatusꢀRegisterꢀbitꢀWELꢀmustꢀequalꢀ1).ꢀTheꢀinstructionꢀisꢀinitiatedꢀbyꢀdrivingꢀtheꢀ
/CSꢀpinꢀlowꢀandꢀshiftingꢀtheꢀinstructionꢀcodeꢀ“52h”ꢀfollowedꢀaꢀ24ꢁbitꢀblockꢀaddressꢀ(A23ꢁA0).ꢀTheꢀ
BlockꢀEraseꢀinstructionꢀsequenceꢀisꢀshownꢀinꢀfigureꢀ17.ꢀ
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Theꢀ/CSꢀpinꢀmustꢀbeꢀdrivenꢀhighꢀafterꢀtheꢀeighthꢀbitꢀofꢀtheꢀlastꢀbyteꢀhasꢀbeenꢀlatched.ꢀIfꢀthisꢀisꢀnotꢀ
doneꢀtheꢀBlockꢀEraseꢀinstructionꢀwillꢀnotꢀbeꢀexecuted.ꢀAfterꢀ/CSꢀisꢀdrivenꢀhigh,ꢀtheꢀselfꢁtimedꢀBlockꢀ
EraseꢀinstructionꢀwillꢀcommenceꢀforꢀaꢀtimeꢀdurationꢀofꢀtBE1ꢀ(SeeꢀACꢀCharacteristics).ꢀWhileꢀtheꢀ
BlockꢀEraseꢀcycleꢀisꢀinꢀprogress,ꢀtheꢀReadꢀStatusꢀRegisterꢀinstructionꢀmayꢀstillꢀbeꢀaccessedꢀforꢀ
checkingꢀ theꢀ statusꢀ ofꢀ theꢀ BUSYꢀ bit.ꢀ Theꢀ BUSYꢀ bitꢀ isꢀ aꢀ 1ꢀ duringꢀ theꢀ Blockꢀ Eraseꢀ cycleꢀ andꢀ
becomesꢀaꢀ0ꢀwhenꢀtheꢀcycleꢀisꢀfinishedꢀandꢀtheꢀdeviceꢀisꢀreadyꢀtoꢀacceptꢀotherꢀinstructionsꢀagain.ꢀ ꢀ
AfterꢀtheꢀSectorꢀEraseꢀcycleꢀhasꢀfinishedꢀtheꢀWriteꢀEnableꢀLatchꢀ(WEL)ꢀbitꢀinꢀStatusꢀRegisterꢀisꢀ
clearedꢀtoꢀ0.TheꢀBlockꢀEraseꢀinstructionꢀwillꢀnotꢀbeꢀexecutedꢀifꢀtheꢀaddressedꢀpageꢀisꢀprotectedꢀbyꢀ
theꢀ Blockꢀ Protectꢀ (SEC,ꢀ TB,ꢀ BP2,ꢀ BP1,ꢀ andꢀ BP0)ꢀ bitsꢀ (seeꢀ Statusꢀ Registerꢀ Memoryꢀ Protectionꢀ
table).ꢀ
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Figureꢀ17.ꢀ32KBꢀBlockꢀEraseꢀInstructionꢀSequenceꢀDiagramꢀ
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preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ
33ꢀ
FIDELIX [ FIDELIX ]
