FM25Q64ꢀ
11.2.16ꢀSectorꢀEraseꢀ(20h)ꢀ
Theꢀ sectorꢀ Eraseꢀinstructionꢀsetsꢀ allꢀ memoryꢀ withinꢀ aꢀ specifiedꢀsectorꢀ (4Kꢁbytes)ꢀtoꢀtheꢀ erasedꢀ
stateꢀofꢀallꢀ1sꢀ(FFh).ꢀAꢀWriteꢀEnableꢀinstructionꢀmustꢀbeꢀexecutedꢀbeforeꢀtheꢀdeviceꢀwillꢀacceptꢀtheꢀ
Sectorꢀ Eraseꢀ Instructionꢀ (Statusꢀ Registerꢀ bitꢀWELꢀ mustꢀ equalꢀ 1).ꢀ Theꢀ instructionꢀ isꢀ initiatedꢀ byꢀ
drivingꢀ theꢀ /CSꢀ pinꢀ lowꢀ andꢀ shiftingꢀ theꢀ instructionꢀ codeꢀ “20h”ꢀ followedꢀ aꢀ 24ꢁbitꢀsectorꢀ addressꢀ
(A23ꢁA0).ꢀTheꢀSectorꢀEraseꢀinstructionꢀsequenceꢀisꢀshownꢀinꢀfigureꢀ16.ꢀ
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Theꢀ/CSꢀpinꢀmustꢀbeꢀdrivenꢀhighꢀafterꢀtheꢀeighthꢀbitꢀofꢀtheꢀlastꢀbyteꢀhasꢀbeenꢀlatched.ꢀIfꢀthisꢀisꢀnotꢀ
doneꢀ theꢀ Sectorꢀ Eraseꢀ instructionꢀ willꢀ notꢀ beꢀ executed.ꢀ Afterꢀ /CSꢀ isꢀ drivenꢀ high,ꢀ theꢀ selfꢁtimedꢀ
SectorꢀEraseꢀinstructionꢀwillꢀcommenceꢀforꢀaꢀtimeꢀdurationꢀofꢀtSEꢀ(SeeꢀACꢀCharacteristics).ꢀWhileꢀ
theꢀSectorꢀEraseꢀcycleꢀisꢀinꢀprogress,ꢀtheꢀReadꢀStatusꢀRegisterꢀinstructionꢀmayꢀstillꢀbeꢀaccessedꢀ
forꢀcheckingꢀtheꢀstatusꢀofꢀtheꢀBUSYꢀbit.ꢀTheꢀBUSYꢀbitꢀisꢀaꢀ1ꢀduringꢀtheꢀSectorꢀEraseꢀcycleꢀandꢀ
becomesꢀaꢀ0ꢀwhenꢀtheꢀcycleꢀisꢀfinishedꢀandꢀtheꢀdeviceꢀisꢀreadyꢀtoꢀacceptꢀotherꢀinstructionsꢀagain.ꢀ
AfterꢀtheꢀSectorꢀEraseꢀcycleꢀhasꢀfinishedꢀtheꢀWriteꢀEnableꢀLatchꢀ(WEL)ꢀbitꢀinꢀStatusꢀRegisterꢀisꢀ
clearedꢀtoꢀ0.ꢀTheꢀSectorꢀEraseꢀinstructionꢀwillꢀnotꢀbeꢀexecutedꢀifꢀtheꢀaddressedꢀpageꢀisꢀprotectedꢀ
byꢀtheꢀBlockꢀProtectꢀ(SEC,ꢀTB,ꢀBP2,ꢀBP1,ꢀandꢀBP0)ꢀbitsꢀ(seeꢀStatusꢀRegisterꢀMemoryꢀprotectionꢀ
table).ꢀ
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Figureꢀ16.ꢀSectorꢀEraseꢀInstructionꢀSequenceꢀDiagramꢀ
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preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ
32ꢀ
FIDELIX [ FIDELIX ]
