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FM25Q64 参数 Datasheet PDF下载

FM25Q64图片预览
型号: FM25Q64
PDF下载: 下载PDF文件 查看货源
内容描述: 64M位串行闪存与4KB扇区,双核和四I / O SPI [64M-BIT Serial Flash Memory with 4KB Sectors, Dual and Quad I/O SPI]
分类和应用: 闪存
文件页数/大小: 61 页 / 2697 K
品牌: FIDELIX [ FIDELIX ]
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Instruction(EBh)  
                                                                                                                        
FM25Q64ꢀ  
11.2.12ꢀFastꢀReadꢀQuadꢀI/Oꢀ(EBh)ꢀ  
TheFastReadQuadI/O(EBh)instructionissimilartotheFastReadDualI/O(BBh)instructionꢀ  
exceptꢀthatꢀaddressꢀandꢀdataꢀbitsꢀareꢀinputꢀandꢀoutputꢀthroughꢀfourꢀpinsꢀIO0,ꢀIO1,ꢀIO2,ꢀandꢀIO3ꢀ ꢀ andꢀ  
fourꢀ Dummyꢀ clockꢀ areꢀ requiredꢀ priorꢀ toꢀ theꢀ dataꢀ output.ꢀ Theꢀ Quadꢀ I/Oꢀ dramaticallyꢀ reducesꢀ  
instructionꢀ overheadꢀ allowingꢀ fasterꢀ randomꢀ accessꢀ forꢀ codeꢀ executingꢀ (XIP)ꢀ directlyꢀ fromꢀ theꢀ  
QuadSPI.TheQuadEnablebit(QE)ofStatusRegisterꢁ2mustbesettoenabletheFastreadꢀ  
QuadꢀI/OꢀInstruction.ꢀ ꢀ  
TheFastReadQuadI/Oinstructioncanfurtherreduceinstructionoverheadthroughsettingtheꢀ  
Modeꢀbitsꢀ(M7ꢁ0)ꢀafterꢀtheꢀinputꢀAddressꢀbitsꢀ(A23ꢁ0),ꢀasꢀshownꢀinꢀfigureꢀ12a.ꢀTheꢀupperꢀnibbleꢀofꢀ  
theꢀ Modeꢀ (M7ꢁ4)ꢀ controlsꢀ theꢀ lengthꢀ ofꢀ theꢀ nextꢀ Fastꢀ Readꢀ Quadꢀ I/Oꢀ instructionꢀ throughꢀ theꢀ  
instructionꢀorꢀexclusionꢀofꢀtheꢀfirstꢀbyteꢀinstructionꢀcode.ꢀTheꢀlowerꢀnibbleꢀbitsꢀofꢀtheꢀModeꢀ(M3ꢁ0)ꢀ  
areꢀdon’tꢀcareꢀ(“X”).ꢀHowever,ꢀtheꢀIOꢀpinsꢀshouldꢀbeꢀhighꢁimpedanceꢀpriorꢀtoꢀtheꢀfallingꢀedgeꢀofꢀtheꢀ  
firstꢀdataꢀoutꢀclock.ꢀ  
IfꢀtheꢀModeꢀbitsꢀ(M7ꢁ0)ꢀequalꢀ“Ax”ꢀhex,ꢀthenꢀtheꢀnextꢀFastꢀReadꢀQuadꢀI/Oꢀinstructionꢀ(afterꢀ/CSꢀisꢀ  
raisedꢀandꢀthenꢀlowered)ꢀdoesꢀnotꢀrequireꢀtheꢀEBhꢀinstructionꢀcode,ꢀasꢀshownꢀinꢀfigureꢀ12b.ꢀThisꢀ  
reducestheinstructionsequencebyeightclocksallowstheaddresstobeimmediatelyenteredꢀ  
afterꢀ /CSꢀ isꢀ assertedꢀ low.ꢀ Ifꢀ theꢀ Modeꢀ bitsꢀ (M7ꢁ0)ꢀ areꢀ anyꢀ valueꢀ otherꢀ thanꢀ “Ax”ꢀ hex,ꢀ theꢀ nextꢀ  
instructionꢀ (afterꢀ /CSꢀ isꢀ raisedꢀ andꢀ thenꢀ lowered)ꢀ requiresꢀ theꢀ firstꢀ byteꢀ instructionꢀ code,ꢀ thusꢀ  
retuningꢀnormalꢀoperation.ꢀAꢀModeꢀBitꢀResetꢀcanꢀbeꢀusedꢀtoꢀresetꢀModeꢀBitsꢀ(M7ꢁ0)ꢀbeforeꢀissuingꢀ  
normalꢀinstructionsꢀ(Seeꢀ11.2.25ꢀforꢀdetailedꢀdescriptions.)ꢀ  
/CS  
Mode3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
Mode0  
CLK  
IOꢀSwitchesꢀfrom  
InputꢀtoꢀOutput  
0
IO  
4
4
0
4
5
0
1
4
5
0
1
4
5
0
1
4
5
0
4
0
1
IO  
5
5
6
1
2
1
5
1
2
IO  
6
2
6
2
6
2
6
2
3
6
7
2
3
6
7
3
IO  
7
3
7
3
7
3
7
3
7
Byte1 Byte2  
M7ꢁ0 Dummy Dummy
A23ꢁ16 A15ꢁ8  
A7ꢁ0  
Figureꢀ12a.ꢀFastꢀReadꢀQuadꢀInput/OutputꢀInstructionꢀSequenceꢀDiagramꢀ(M7ꢁ0ꢀ=ꢀ0xhꢀorꢀNOTꢀAxh)ꢀ  
preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ  
27ꢀ  
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