FM25Q64ꢀ
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11.2.11ꢀFastꢀReadꢀDualꢀI/Oꢀ(BBh)ꢀ
TheꢀFastꢀReadꢀDualꢀI/Oꢀ(BBh)ꢀinstructionꢀallowsꢀforꢀimprovedꢀrandomꢀaccessꢀwhileꢀmaintainingꢀ
twoꢀ IOꢀ pins,ꢀ IO0ꢀ andꢀ IO1.ꢀ Itꢀ isꢀ similarꢀ toꢀ theꢀ Fastꢀ Readꢀ Outputꢀ (0Bh)ꢀ instructionꢀ butꢀ withꢀ theꢀ
capabilityꢀ toꢀ inputꢀ theꢀ Addressꢀ bitsꢀ (A23ꢁ0)ꢀ twoꢀ bitsꢀ andꢀ outputꢀ dataꢀ twoꢀ bitsꢀ perꢀ clock.ꢀ Thisꢀ
reducedꢀ instructionꢀ overheadꢀ mayꢀ allowꢀ forꢀ codeꢀ executionꢀ (XIP)ꢀ directlyꢀ fromꢀ theꢀ Dualꢀ SPIꢀ inꢀ
someꢀapplications.ꢀ ꢀ
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Theꢀ Fastꢀ Readꢀ Dualꢀ I/Oꢀ instructionꢀ canꢀ furtherꢀ reduceꢀ instructionꢀ overheadꢀ throughꢀsettingꢀ theꢀ
Modeꢀbitsꢀ(M7ꢁ0)ꢀafterꢀtheꢀinputꢀAddressꢀbitsꢀ(A23ꢁ0),ꢀasꢀshownꢀinꢀfigureꢀ11a.ꢀTheꢀupperꢀnibbleꢀofꢀ
theꢀ Modeꢀ (M7ꢁ4)ꢀ controlsꢀ theꢀ lengthꢀ ofꢀ theꢀ nextꢀ Fastꢀ Readꢀ Dualꢀ I/Oꢀ instructionꢀ throughꢀ theꢀ
instructionꢀorꢀexclusionꢀofꢀtheꢀfirstꢀbyteꢀinstructionꢀcode.ꢀTheꢀlowerꢀnibbleꢀbitsꢀofꢀtheꢀModeꢀ(M3ꢁ0)ꢀ
areꢀdon’tꢀcareꢀ(“X”),ꢀHowever,ꢀtheꢀIOꢀpinsꢀshouldꢀbeꢀhighꢁimpedanceꢀpriorꢀtoꢀtheꢀfallingꢀedgeꢀofꢀtheꢀ
firstꢀdataꢀoutꢀclock.ꢀ
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IfꢀtheꢀModeꢀbitsꢀ(M7ꢁ0)ꢀequalꢀ“Ax”ꢀhex,ꢀthenꢀtheꢀnextꢀFastꢀDualꢀI/Oꢀinstructionꢀ(afterꢀ/CSꢀisꢀraisedꢀ
andꢀthenꢀlowered)ꢀdoesꢀnotꢀrequireꢀtheꢀBBhꢀinstructionꢀcode,ꢀasꢀshownꢀinꢀfigureꢀ11b.ꢀThisꢀreducesꢀ
theꢀinstructionꢀsequenceꢀbyꢀeightꢀclocksꢀandꢀallowsꢀtheꢀaddressꢀtoꢀbeꢀimmediatelyꢀenteredꢀafterꢀ
/CSꢀisꢀassertedꢀlow.ꢀIfꢀModeꢀbitsꢀ(M7ꢁ0)ꢀareꢀanyꢀvalueꢀotherꢀ“Ax”ꢀhex,ꢀtheꢀnextꢀinstructionꢀ(afterꢀ/CSꢀ
isꢀ raisedꢀ andꢀ thenꢀ lowered)ꢀ requiresꢀ theꢀ firstꢀ byteꢀ instructionꢀ code,ꢀ thusꢀ returningꢀ toꢀ normalꢀ
operation.ꢀ Aꢀ Modeꢀ Bitꢀ Resetꢀ instructionꢀ canꢀ beꢀ usedꢀ toꢀ resetꢀ Modeꢀ Bitsꢀ (M7ꢁ0)ꢀ beforeꢀ issuingꢀ
normalꢀinstructionsꢀ(Seeꢀ11.2.25ꢀforꢀdetailedꢀdescriptions).ꢀ
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Figureꢀ11a.ꢀFastꢀReadꢀDualꢀInput/OutputꢀInstructionꢀSequenceꢀDiagramꢀ(M7ꢁ0ꢀ=ꢀ0xhꢀorꢀNOTꢀAxh)ꢀ
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preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ
25ꢀ
FIDELIX [ FIDELIX ]
