FM25Q64ꢀ
ꢀ
11.2.4ꢀWriteꢀEnableꢀ(06h)ꢀ
Theꢀ Writeꢀ Enableꢀ instructionꢀ (Figureꢀ 4)ꢀ setsꢀ theꢀ Writeꢀ Enableꢀ Latchꢀ (WEL)ꢀ bitꢀ inꢀ theꢀ Statusꢀ
Registerꢀtoꢀaꢀ1.ꢀTheꢀWELꢀbitꢀmustꢀbeꢀsetꢀpriorꢀtoꢀeveryꢀPageꢀProgram,ꢀSectorꢀErase,ꢀBlockꢀErase,ꢀ
ChipꢀEraseꢀandꢀWriteꢀStatusꢀRegisterꢀinstruction.ꢀTheꢀWriteꢀEnableꢀinstructionꢀisꢀenteredꢀbyꢀdrivingꢀ
/CSꢀlow,ꢀshiftingꢀtheꢀinstructionꢀcodeꢀ“06h”ꢀintoꢀDataꢀInputꢀ(DI)ꢀpinꢀonꢀtheꢀrisingꢀedgeꢀofꢀCLK,ꢀandꢀ
thenꢀdrivingꢀ/CSꢀhigh.ꢀ
ꢀ
/CS
Modeꢀ 3
Modeꢀ 0
Modeꢀ 3
Modeꢀ 0
0
1
2
3
4
5
6
7
CLK
Instructionꢀ (06 h)
DI
HighꢀImpedance
DO
Figureꢀ4.ꢀWriteꢀEnableꢀInstructionꢀSequenceꢀDiagramꢀ
ꢀ
ꢀ
11.2.5ꢀWriteꢀEnableꢀforꢀVolatileꢀStatusꢀRegisterꢀ(50h)ꢀ
TheꢀnonꢁvolatileꢀStatusꢀRegisterꢀbitsꢀdescribedꢀinꢀsectionꢀ12.1ꢀcanꢀalsoꢀbeꢀwrittenꢀtoꢀasꢀvolatileꢀbits.ꢀ
Thisꢀ givesꢀ moreꢀ flexibilityꢀ toꢀ changeꢀ theꢀ systemꢀ configurationꢀ andꢀ memoryꢀ protectionꢀ schemesꢀ
quicklyꢀwithoutꢀwaitingꢀforꢀtheꢀtypicalꢀnonꢁvolatileꢀbitꢀwriteꢀcyclesꢀorꢀaffectingꢀtheꢀenduranceꢀofꢀtheꢀ
StatusꢀRegisterꢀnonꢁvolatileꢀbits.ꢀToꢀwriteꢀtheꢀvolatileꢀvaluesꢀintoꢀtheꢀStatusꢀRegisterꢀbits,ꢀtheꢀWriteꢀ
EnableꢀforꢀVolatileꢀStatusꢀRegisterꢀ(50h)ꢀinstructionꢀmustꢀbeꢀissuedꢀpriorꢀtoꢀaꢀWriteꢀStatusꢀRegisterꢀ
(01h)ꢀ instruction.ꢀWriteꢀ Enableꢀ forꢀ Volatileꢀ Statusꢀ Registerꢀ instructionꢀ (Figureꢀ5)ꢀ willꢀ notꢀ setꢀ theꢀ
WriteꢀEnableꢀLatchꢀ(WEL)ꢀbit,ꢀitꢀisꢀonlyꢀvalidꢀforꢀtheꢀWriteꢀStatusꢀRegisterꢀinstructionꢀtoꢀchangeꢀtheꢀ
volatileꢀStatusꢀRegisterꢀbitꢀvaluesꢀ
ꢀ
/CS
Modeꢀ 3
Modeꢀ 0
Modeꢀ 3
Modeꢀ 0
0
1
2
3
4
5
6
7
CLK
Instructionꢀ (06 h)
DI
HighꢀImpedance
DO
ꢀ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ Figureꢀ5.ꢀWriteꢀEnableꢀforꢀVolatileꢀStatusꢀRegisterꢀInstructionꢀSequenceꢀDiagramꢀ
ꢀ
preliminary(Aug.18.2010)ꢀ ꢀ ꢀ ꢀ
20ꢀ
FIDELIX [ FIDELIX ]
