May 1996
NDS9435A
Single P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited
for low voltage applications such as notebook computer
power management and other battery powered circuits
where fast switching, low in-line power loss, and resistance
to transients are needed.
Features
-5.3A, -30V. R
DS(ON)
= 0.05
Ω
@ V
GS
= -10V
R
DS(ON)
= 0.07
Ω
@ V
GS
= -6V
R
DS(ON)
= 0.09
Ω
@ V
GS
= -4.5V.
High density cell design for extremely low R
DS(ON).
High power and current handling capability in a widely
used surface mount package.
____________________________________________________________________________________________
D
D
D
D
5
6
S
G
7
8
4
3
2
1
SO-8
pin
1
S
S
Absolute Maximum Ratings
Symbol
Parameter
T
A
= 25°C unless otherwise noted
NDS9435A
Units
V
DSS
V
GSS
I
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
(Note 1a)
-30
± 20
± 5.3
± 20
(Note 1a)
(Note 1b)
(Note 1c)
V
V
A
P
D
Maximum Power Dissipation
2.5
1.2
1
-55 to 150
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
°C/W
°C/W
© 1999 Fairchild Semiconductor Corporation
NDS9435A Rev B
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
