June1996
NDC632P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as notebook computer power
management and other battery powered circuits
where fast high-side switching, and low in-line power
loss are needed in a very small outline surface
mount package.
Features
-2.7A, -20V. R
DS(ON)
= 0.14
Ω
@ V
GS
= -4.5V
R
DS(ON)
= 0.2
Ω
@ V
GS
= -2.7V.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
___________________________________________________________________________________________
4
3
5
2
6
1
SuperSOT
TM
-6
Absolute Maximum Ratings
Symbol Parameter
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
T
A
= 25°C unless otherwise noted
NDC632P
-20
-8
-2.7
-10
(Note 1a)
(Note 1b)
(Note 1c)
Units
V
V
A
1.6
1
0.8
-55 to 150
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
30
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDC632P Rev. B1
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
