ML6554
PRODUCT SPECIFICATION
DRAWING NUMBER
ENG-CB-1007 REV A
Applicable Jedec Spec
JC 51-X (Note 1)
(Proposed Spec)
Substrate Material
FR-4
114.3 x 76.2mm
55 x 65mm
73 x 73mm
1.6 mm
Dimensions (LxW) (Overall)
Dimensions (LxW) (Metallization)
Dimensions (LxW) (Inner Planes)
Thickness
Pitch
1.27mm
Stackup (# Signal Layers, # Cu Planes)
Cu Trace Coverage (Signal Layer)
Cu Coverage (Internal Layer)
Trace Width (Spec/Measured)
Trace Cu Thickness (Spec/Measured)
Inner Cu Thickness (Spec/Measured)
Build #
1S2P
12ꢀ
100ꢀ
235.5 25.5/288µm
70 14/67µm
35 3.5/31µm
C1797
Note 1: Proposed Spec "Thermal Test Board with Two Internal Solid Copper Planes for leaded Surface Mount Packages".
Figure 12. Test Board Layout for Θ vs. Airflow
JA
Table 3. Termination Solutions Summary By Buss Type
Industry
System
Components
Driving
Method
Fairchild
Solutions
Bus
GTL+
Description
VDDQ
VTT
VREF
Gunning
Transceiver
Bus Plus
Open Drain 5v or 3.3V 1.5V 10ꢀ 1.0V 2ꢀ ML6554CU;
300 to 500MHz
Processor;
PC Chipsets;
GTLP 16xxx
Buffers;
Note 10
Note12
Note 11 Mode: VREF
Input = 1.5V,
VCC = 5V
Fairchild,
Texas Instr.
SSTL_2
Series Stub
Terminated
Logic for 2V
Symmetric 2.5V 10ꢀ
Drive,
Series
0.5x
(VDDQ
3ꢀ
2.5V
ML6554CU
or ML6553CS;
Mode: VREF
SSTL SDRAM;
Hitachi,
Fujitsu,
)
Resistance
Input = Floating NEC, Micro,
or Forced,
Mitsubishi
VCC = 3.3V
RAMBUS RAMBUS
Signaling
Open Drain
None
Specified
2.5V
2.0V
3.3V
ML6553CS;
Mode: VREF
Input = Open,
VCC = VDDQ
nDRAM,
RAMBUS,
Intel, Toshiba
Logic
LV-TTL
Low Voltage Symmetric
TTL Logic or Drive
PECL or
3.3 10ꢀ
VDDQ/2
ML6553CS;
Mode: VREF
Input = Open,
VCC = VDDQ
Processors or
backplanes;
LV-TTL
3.3V VME
SDRAM,
EDO RAM
12
REV. 1.1.3 3/8/02
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
