欢迎访问ic37.com |
会员登录 免费注册
发布采购

ML6554CU 参数 Datasheet PDF下载

ML6554CU图片预览
型号: ML6554CU
PDF下载: 下载PDF文件 查看货源
内容描述: 3A总线终端稳压器 [3A Bus Termination Regulator]
分类和应用: 总线通信稳压器驱动程序和接口接口集成电路光电二极管
文件页数/大小: 14 页 / 387 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
 浏览型号ML6554CU的Datasheet PDF文件第2页浏览型号ML6554CU的Datasheet PDF文件第3页浏览型号ML6554CU的Datasheet PDF文件第4页浏览型号ML6554CU的Datasheet PDF文件第5页浏览型号ML6554CU的Datasheet PDF文件第6页浏览型号ML6554CU的Datasheet PDF文件第7页浏览型号ML6554CU的Datasheet PDF文件第8页浏览型号ML6554CU的Datasheet PDF文件第9页  
www.fairchildsemi.com
ML6554
3A Bus Termination Regulator
Features
• Can source and sink up to 3A, no heat sink required
• Integrated Power MOSFETs
• Generates termination voltages for DDR SDRAM,
SSTL-2 SDRAM, SGRAM, or equivalent memories
• Generates termination voltages for active termination
schemes for DDR SDRAM, GTL+, Rambus, VME,
LV-TTL, HSTL, PECL and other high speed logic
• V
REF
input available for external voltage divider
• Separate voltages for V
CCQ
and PV
DD
• Buffered V
REF
output
• V
OUT
of ±3% or less at 3A
• Minimum external components
• Shutdown for standby or suspend mode operation
• 0° to +70°C and -40° to +85°C temperature ranges
available
• Thermal Shutdown
130ºC
Description
The ML6554 switching regulator is designed to convert volt-
age supplies ranging from 2.3V to 4V into a desired output
voltage or termination voltage for various applications. The
ML6554 can be implemented to produce regulated output
voltages in two different modes. In the default mode, when
the V
REF
pin is open, the ML6554 output voltage is 50% of
the voltage applied to V
CCQ
. The ML6554 can also be used
to produce various user-defined voltages by forcing a voltage
on the VREF
IN
pin. In this case, the output voltage follows
the input VREF
IN
voltage. The switching regulator is capa-
ble of sourcing or sinking up to 3A of current while regulat-
ing an output V
TT
voltage to within 3% or less.
The ML6554, used in conjunction with series termination
resisitors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator can
be used as a termination voltage for other bus interface
standards such as DDR SDRAM, SSTL, CMOS, Rambus
,
GTL+, VME, LV-CMOS, LV-TTL, HSTL and PECL.
Block Diagram
15
VCCQ
16
AVCC
14
VREFOUT
1
9
VDD
VDD
12
SHDN
2
PVDD1
7
PVDD2
VL1
(VOUT)
3
OSCILLATOR/
RAMP
GENERATOR
200kΩ
+
VREF BUFFER
VREFIN
11
200kΩ
AGND
13
+
R
+
ERROR AMP
RAMP
COMPARATOR
Q
S
Q
6
VL2
(VOUT)
VFB
10
8
DGND
4
PGND1
5
PGND2
REV. 1.1.3 3/8/02