ML4800
PRODUCT SPECIFICATION
Pin Configuration
ML4800
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N)
IEAO 1
IAC 2
ISENSE 3
VRMS 4
SS 5
VDC 6
RAMP 1 7
RAMP 2 8
16 VEAO
15 VFB
14 VREF
13 VCC
12 PFC OUT
11 PWM OUT
10 GND
9
DC ILIMIT
TOP VIEW
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
IEAO
I
AC
I
SENSE
V
RMS
SS
V
DC
RAMP 1
RAMP 2
DC I
LIMIT
GND
PWM OUT
PFC OUT
V
CC
V
REF
V
FB
VEAO
Function
Slew rate enhanced PFC transconductance error amplifier output
PFC AC line reference input to Gain Modulator
Current sense input to the PFC Gain Modulator
PFC Gain Modulator RMS line voltage compensation input
Connection point for the PWM soft start capacitor
PWM voltage feedback input
Oscillator timing node; timing set by R
T
C
T
When in current mode, this pin functions as the current sense input; when in voltage mode,
it is the PWM modulation ramp input.
PWM cycle-by-cycle current limit comparator input
Ground
PWM driver output
PFC driver output
Positive supply
Buffered output for the internal 7.5V reference
PFC transconductance voltage error amplifier input
PFC transconductance voltage error amplifier output
2
REV. 1.0.5 9/25/01
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
