KA3842B/KA3843B/KA3844B/KA3845B
Shutdown of the KA3842B can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage
two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram).
The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at
pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SOR which
will be reset by cycling Voc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
Figure 9. Slope Compensation
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for
converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch
spikes.
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. TEMPERATURE DRIFT (Vref)
Figure 11. TEMPERATURE DRIFT (Ist)
TEMPERATURE (°C)
Figure 12. TEMPERATURE DRIFT (Icc)
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FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
