Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
April 2013
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M
High-Speed 10 MBit/s Logic Gate Optocouplers
Features
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Description
The 6N137M, HCPL2601M, HCPL2611M single-channel
and HCPL2630M, HCPL2631M dual-channel optocou-
plers consist of a 850 nm AlGaAS LED, optically coupled
to a very high speed integrated photo-detector logic gate
with a strobable output. This output features an open col-
lector, thereby permitting wired OR outputs. The
switching parameters are guaranteed over the tempera-
ture range of -40°C to +85°C. A maximum input signal of
5 mA will provide a minimum output sink current of
13 mA (fan out of 8).
An internal noise shield provides superior common
mode rejection of typically 10 kV/µs. The HCPL2601M
and HCPL2631M has a minimum CMR of 5 kV/µs. The
HCPL2611M has a minimum CMR of 10 kV/µs.
Very High Speed – 10 MBit/s
Superior CMR – 10 kV/µs
Fan-out of 8 Over -40°C to +85°C
Logic Gate Output
Strobable Output
Wired OR-open Collector
U.L. Recognized (File # E90700, Vol. 2)
Applications
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Ground Loop Elimination
LSTTL to TTL, LSTTL or 5 V CMOS
Line Receiver, Data Transmission
Data Multiplexing
Switching Power Supplies
Pulse Transformer Replacement
Computer-peripheral Interface
Schematics
Package Outlines
N/C 1
8 V
CC
8
+ 1
V
F1
8 V
CC
1
8
1
+ 2
V
F
_
3
7 V
E
_ 2
7 V
01
8
6 V
O
_
V
3
6 V
02
8
1
1
F2
Figure 2. Package Options
5 GND
N/C 4
5 GND
+ 4
Truth Table
(Positive Logic)
Input
Enable
H
H
L
L
NC
NC
Output
L
H
H
H
L
H
www.fairchildsemi.com
6N137M
HCPL2601M
HCPL2611M
H
HCPL2630M
HCPL2631M
(Preliminary)
L
H
L
H
L
A 0.1µF bypass capacitor must be connected between pins 8 and 5
(1)
.
Figure 1. Schematics
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
