August 1997
FDV303N
Digital FET, N-Channel
General Description
These N-Channel enhancement mode field effect transistors are
produced using Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is tailored to minimize
on-state resistance at low gate drive conditions. This device is
designed especially for application in battery circuits using either
one lithium or three cadmium or NMH cells. It can be used as an
inverter or for high-efficiency miniature discrete DC/DC
conversion in compact portable electronic devices like cellular
phones and pagers. This device has excellent on-state
resistance even at gate drive voltages as low as 2.5 volts.
Features
25 V, 0.68 A continuous, 2 A Peak.
R
DS(ON)
= 0.45
Ω
@ V
GS
= 4.5 V
R
DS(ON)
= 0.6
Ω
@ V
GS
= 2.7 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Compact industry standard SOT-23 surface mount
package.
Alternative to TN0200T and TN0201T.
SOT-23
Mark:303
SuperSOT -6
TM
SuperSOT -8
TM
SO-8
SOT-223
SOIC-16
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
ESD
Parameter
T
A
= 25
o
C unless other wise noted
FDV303N
25
8
Units
V
V
A
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage, V
IN
Drain/Output Current
- Continuous
- Pulsed
Maximum Power Dissipation
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
0.68
2
0.35
-55 to 150
6.0
W
°C
kV
THERMAL CHARACTERISTICS
R
θ
JA
357
°C/W
© 1997 Fairchild Semiconductor Corporation
FDV303N Rev.D1
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
