March 1998
FDC654P
P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low
voltage applications such as cellular phone and notebook
computer power management and other battery powered
circuits where high-side switching, and low in-line power
loss are needed in a very small outline surface mount
package.
Features
-3.6 A, -30 V. R
DS(ON)
= 0.075
Ω
@ V
GS
= -10 V
R
DS(ON)
= 0.125
Ω
@ V
GS
= -4.5 V.
SuperSOT
TM
-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current capability.
SOT-23
SuperSOT -6
TM
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
S
D
D
1
6
4
.65
G
pin
1
2
5
D
D
SuperSOT
TM
-6
3
4
Absolute Maximum Ratings
T
A
= 25°C unless otherwise note
Symbol Parameter
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1a)
FDC654P
-30
±20
-3.6
-10
1.6
0.8
-55 to 150
Units
V
V
A
W
T
J
,T
STG
R
θJA
R
θJC
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
30
°C/W
°C/W
© 1998 Fairchild Semiconductor Corporation
FDC654P Rev.C
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
