Electrical Characteristics
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative
out of the device.
Symbol
Supply
VDD
Parameter
Conditions
Min. Typ. Max. Unit
Operating Range
4.5
18.0
0.95
4.3
V
mA
V
IDD
Supply Current, Inputs Not Connected
Turn-On Voltage
0.70
3.9
VON
INA = VDD, INB = 0V
INA = VDD, INB = 0V
3.5
3.3
VOFF
Turn-Off Voltage
3.7
4.1
V
Inputs
VIL_T
INx Logic Low Threshold
INx Logic High Threshold
Non-Inverting Input
0.8
1.2
1.6
V
V
VIH_T
IIN+
2.0
175.0
1.5
IN from 0 to VDD
IN from 0 to VDD
-1.5
-175.0
0.2
µA
µA
V
IIN-
Inverting Input
VHYS_T
Output
TTL Logic Hysteresis Voltage
0.4
0.8
OUTx at VDD/2,
ISINK
OUT Current, Mid-Voltage, Sinking(8)
4.3
A
A
CLOAD=0.22µF, f=1kHz
OUTx at VDD/2,
ISOURCE
IPK_SINK
OUT Current, Mid-Voltage, Sourcing(8)
OUT Current, Peak, Sinking(8)
-2.8
CLOAD=0.22µF, f=1kHz
CLOAD=0.22µF, f=1kHz
CLOAD=0.22µF, f=1kHz
CLOAD=2200pF
5
-5
12
9
A
A
IPK_SOURCE OUT Current, Peak, Sourcing(8)
tRISE
tFALL
Output Rise Time(9)
20
17
29
ns
ns
ns
Output Fall Time(9)
CLOAD=2200pF
tD1, tD2
Output Propagation Delay, TTL Inputs(9)
0 - 5VIN, 1V/ns Slew Rate
9
17
INA=INB, OUTA and OUTB
at 50% Point
Propagation Matching Between Channels
Output Reverse Current Withstand(8)
2
4
ns
IRVS
500
mA
Notes:
8. Not tested in production.
9. See Timing Diagrams of Figure 6 and Figure 7.
Figure 6. Non-Inverting Timing Diagram
Figure 7. Inverting Timing Diagram
© 2008 Fairchild Semiconductor Corporation
FAN3213 / FAN3214 • Rev. 1.0.2
www.fairchildsemi.com
6
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
