CD4069UBC Inverter Circuits
October 1987
Revised January 1999
CD4069UBC
Inverter Circuits
General Description
The CD4069UB consists of six inverter circuits and is man-
ufactured using complementary MOS (CMOS) to achieve
wide power supply operating range, low power consump-
tion, high noise immunity, and symmetric controlled rise
and fall times.
This device is intended for all general purpose inverter
applications where the special characteristics of the
MM74C901, MM74C907, and CD4049A Hex Inverter/Buff-
ers are not required. In those applications requiring larger
noise immunity the MM74C14 or MM74C914 Hex Schmitt
Trigger is suggested.
All inputs are protected from damage due to static dis-
charge by diode clamps to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
High noise immunity:
3.0V to 15V
0.45 V
DD
typ.
s
Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s
Equivalent to MM74C04
Ordering Code:
Order Number
CD4069UBCM
CD4069UBCSJ
CD4069UBCN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Schematic Diagram
© 1999 Fairchild Semiconductor Corporation
DS005975.prf
www.fairchildsemi.com
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