May 1995
BSS138
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. These products
have been designed to minimize on-state resistance
while provide rugged, reliable, and fast switching
performance. These products are particularly suited for
low voltage, low current applications such as small
servo motor control, power MOSFET gate drivers, and
other switching applications.
Features
0.22 A, 50V. R
DS(ON)
= 3.5
Ω
@ V
GS
= 10V.
High density cell design for extremely low R
DS(ON)
.
Rugged and Relaible
Compact industry standard SOT-23 surface mount
package.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
DGR
V
GSS
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
BSS138
50
50
± 20
± 40
0.22
0.88
0.36
2.8
-55 to 150
300
Units
V
V
V
Drain-Gate Voltage (R
GS
< 20K
Ω
)
Gate-Source Voltage - Continuous
- Non Repetitive (T
P
< 50 µS)
I
D
P
D
T
J
,T
STG
T
L
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
Derate Above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering
Purposes, 1/16" from Case for 10 Seconds
A
W
mW/°C
°C
°C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction to Ambient
350
°C/W
© 1997 Fairchild Semiconductor Corporation
BSS138 Rev. A1
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
