FAN5026 — Dual DDR / Dual-Output PWM Controller
Pin Definitions
Pin #
11
12
17
13
Name
ILIM1
SS1
SS2
DDR
Description
Current Limit 1.
A resistor from this pin to GND sets the current limit.
Soft Start.
A capacitor from this pin to GND programs the slew rate of the converter during
initialization. During initialization, this pin is charged with a 5mA current source.
DDR Mode Control.
HIGH = DDR Mode. LOW = two separate regulators operating 180
degrees out of phase.
Input Voltage.
Normally connected to the battery, providing voltage feedforward to set the
amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V
input, connect through 100KΩ resistor to ground, which sets the appropriate ramp gain and
synchronizes the channels 90° out of phase.
Power-Good Flag.
An open-drain output that pulls LOW when V
SEN
is outside a ±10% range of
the 0.9V reference.
Power-Good 2.
When not in DDR Mode, open-drain output that pulls LOW when the V
OUT
is
out of regulation or in a fault condition.
14
VIN
15
PG1
16
PG2 /
REF2OUT
Reference Out 2.
When in DDR Mode, provides a buffered output of REF2. Typically used as
the V
DDQ/2
reference.
ILIM2 /
REF2
VCC
Current Limit 2.
When not in DDR Mode, a resistor from this pin to GND sets the current limit.
Reference
for reg #2 when in DDR Mode. Typically set to V
OUT1/2
.
VCC.
This pin powers the chip as well as the LDRV buffers. The IC starts to operate when
voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V
(UVLO falling).
18
28
Block Diagram
Figure 4. IC Block Diagram
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
www.fairchildsemi.com
4
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