FAN5026 — Dual DDR / Dual-Output PWM Controller
For this type of modulator, a Type-2 compensation
circuit is usually sufficient. To reduce the number of
external components and simplify the design, the PWM
controller has an internally compensated error amplifier.
Figure 13 shows a Type-2 amplifier and its response
with the responses of a current-mode modulator and
the converter. The Type-2 amplifier, in addition to the
pole at the origin, has a zero-pole pair that causes a flat
gain region at frequencies between zero and the pole.
If a larger inductor value or low-ESR values are
required by the application, additional phase margin can
be achieved by putting a zero at the LC crossover
frequency. This can be achieved with a capacitor across
the feedback resistor (e.g. R5 from Figure 6), as shown
in Figure 14.
L(OUT)
R5
VSEN
C(Z)
V
OUT
C(OUT)
f
Z
=
f
P
=
1
=
6kHz
2
π
R
2
C
1
1
=
600kHz
2
π
R
2
C
2
(7)
R6
(8)
Figure 14.
Improving Phase Margin
This region is also associated with phase “bump” or
reduced phase shift. The amount of phase-shift
reduction depends on the width of the region of flat gain
and has a maximum value of 90°. To further simplify the
converter compensation, the modulator gain is kept
independent of the input voltage variation by providing
feedforward of V
IN
to the oscillator ramp.
The zero frequency, the amplifier high-frequency gain,
and the modulator gain are chosen to satisfy most
typical applications. The crossover frequency appears
at the point where the modulator attenuation equals the
amplifier high-frequency gain. The system designer
must specify the output filter capacitors to position the
load main pole somewhere within a decade lower than
the amplifier zero frequency. With this type of
compensation, plenty of phase margin is achieved due
to zero-pole pair phase “boost.”
C2
R2
R1
The optimal value of C(Z) is:
C(Z)
=
L(OUT)
×
C(OUT)
R
(9)
Protections
The converter output is monitored and protected
against extreme overload, short-circuit, over-voltage,
and under-voltage conditions.
A sustained overload on an output sets the PGx pin
LOW and latches-off the regulator on which the fault
occurs. Operation can be restored by cycling the V
CC
voltage or by toggling the EN pin.
If V
OUT
drops below the under-voltage threshold, the
regulator shuts down immediately.
Over-Current Sensing
If the circuit’s current-limit signal (“ILIM det” in Figure
12) is HIGH at the beginning of a clock cycle, a pulse-
skipping circuit is activated and HDRV is inhibited. The
circuit continues to pulse skip in this manner for the
next eight clock cycles. If, at any time from the ninth to
the sixteenth clock cycle, the ILIM det is again reached;
the over-current protection latch is set, disabling the
regulator. If ILIM det does not occur between cycles
nine and sixteen, normal operation is restored and the
over-current circuit resets itself.
C1
V
IN
REF
EA Out
C
on
err
or
ve
am
rt e
p
r
modul ator
18
14
0
f
P0
f
Z
f
P
Figure 13.
Compensation
Conditional stability may occur only when the main load
pole is positioned too much to the left on the frequency
axis due to excessive output filter capacitance. In this
case, an ESR zero placed within the 10kHz to 50kHz
range gives some additional phase boost. Fortunately,
there is an opposite trend in mobile applications to keep
the output capacitor as small as possible.
Figure 15.
© 2005 Fairchild Semiconductor Corporation
FAN5026 • Rev. 1.0.8
Over-Current Protection Waveforms
www.fairchildsemi.com
12
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
