74F74
Unit Loading/Fan Out
U.L.
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
Description
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.8 mA
20
µ
A/
−
1.8 mA
−
1 mA/20 mA
Truth Table
Inputs
S
D
L
H
L
H
H
H
C
D
H
L
L
H
H
H
CP
X
X
D
X
X
X
h
l
X
Outputs
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
L
X
H (h)
=
HIGH Voltage Level
L (l)
=
LOW Voltage Level
X
=
Immaterial
Q
0
=
Previous Q (Q) before LOW-to-HIGH Clock Transition
Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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