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74ABT245CMSA 参数 Datasheet PDF下载

74ABT245CMSA图片预览
型号: 74ABT245CMSA
PDF下载: 下载PDF文件 查看货源
内容描述: 八路双向收发器与3态输出 [Octal Bi-Directional Transceiver with 3-STATE Outputs]
分类和应用: 总线驱动器总线收发器逻辑集成电路光电二极管信息通信管理
文件页数/大小: 11 页 / 133 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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74ABT245
DC Electrical Characteristics
(SOIC package)
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Min
Typ
0.7
Max
1.0
Units
V
V
V
V
0.6
V
V
CC
5.0
5.0
5.0
5.0
5.0
T
A
T
A
T
A
T
A
T
A
Conditions
C
L
50 pF, R
L
500
:
25
q
C (Note 4)
25
q
C (Note 4)
25
q
C (Note 6)
25
q
C (Note 5)
25
q
C (Note 5)

1.3
2.7
2.0

1.0
3.1
1.7
0.9
Note 4:
Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5:
Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
Note 6:
Max number of outputs defined as (n). n

1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package)
T
A
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
Data to Outputs
Output Enable
Time
Output Disable
Time
1.0
1.0
1.5
1.5
1.0
1.0
V
CC
C
L

25
q
C

5V
50 pF
Typ
2.1
2.4
3.2
3.7
3.6
3.3
Max
3.6
3.6
6.0
6.0
6.1
5.6
T
A

55
q
C to

125
q
C
V
CC
C
L
Min
1.0
1.0
1.0
2.0
1.7
1.7
4.5V–5.5V
50 pF
Max
4.8
4.8
6.7
7.5
7.4
6.5
T
A

40
q
C to

85
q
C
4.5V–5.5V
50 pF
Max
3.6
3.6
6.0
6.0
6.1
5.6
ns
ns
ns
Units
C
L
V
CC
Min
1.0
1.0
1.5
1.5
1.0
1.0
Extended AC Electrical Characteristics
(SOIC package)

40
q
C to

85
q
C
V
CC
Symbol
Parameter
C
L
4.5V–5.5V
50 pF
T
A

40
q
C to

85
q
C
4.5V–5.5V
250 pF
C
L
T
A

40
q
C to

85
q
C
4.5V–5.5V
250 pF
Units
C
L
V
CC
V
CC
8 Outputs Switching
(Note 7)
Min
f
TOGGLE
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Max Toggle Frequency
Propagation Delay
Data to Outputs
Output Enable Time
1.5
1.5
1.5
1.5
1.0
1.0
Typ
100
5.0
5.0
6.5
6.5
6.5
5.6
Max
1 Output Switching
(Note 8)
Min
1.5
1.5
2.5
2.5
(Note 10)
Max
6.0
6.0
7.5
7.5
8 Outputs Switching
(Note 9)
Min
2.5
2.5
2.5
2.5
Max
MHz
8.5
8.5
9.5
11.0
(Note 10)
ns
ns
ns
Note 7:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 8:
This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 9:
This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10:
The 3-STATE delays are dominated by the RC network (500
:
, 250 pF) on the output and have been excluded from the datasheet.
www.fairchildsemi.com
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