6N138,6N139
Switching Specifications
(Ta=25°C, V
CC
=5V, unless otherwise specified)
Characteristic
Propagation delay
time to logic low
at output
(Note 6, 8)
6N139
6N138
6N139
6N138
CM
H
2
Symbol
Test
Circuit
Test Condition
I
F
=0.5mA, R
L
=4.7kΩ
t
pHL
(*)
1
I
F
=12mA, R
L
=270Ω
I
F
=1.6mA, R
L
=2.2kΩ
I
F
=0.5mA, R
L
=4.7kΩ
t
pLH
(*)
1
I
F
=12mA, R
L
=270Ω
I
F
=1.6mA, R
L
=2.2kΩ
I
F
=0mA, R
L
=2.2kΩ
V
CM
=400V
p−p
I
F
=1.6mA
R
L
=2.2kΩ
V
CM
=400V
p−p
Min.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Typ.
5
0.2
1
5
1
4
500
Max.
25
1
10
60
7
35
⎯
V /
μs
μs
μs
Unit
Propagation delay
time to logic high
at output
(Note 6, 8)
Common mode transient
immunity at logic high
level output
Common mode transient
immunity at logic low
level output
(Note 9)
(Note 9)
CM
L
2
⎯
−500
⎯
V /
μs
(*)JEDEC registered data.
(Note 1):
(Note 2):
(Note 3):
(Note 4):
(Note 5):
(Note 6):
(Note 7):
(Note 8):
(Note 9):
Derate linearly above 50°C free−air temperature at a rate of 0.4mA / °C
Derate linearly above 50°C free−air temperature at a rate of 0.7mW / °C
Derate linearly above 25°C free−air temperature at a rate of 0.7mA / °C
Derate linearly above 25°C free−air temperature at a rate of 2.0mW / °C
DC CURRENT TRANSFER RATIO is defined as the ratio of output collector current, I
O
, to the forward
LED input current, I
F
, times 100%.
Pin 7 open.
Device considered a two−terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7 and 8
shorted together.
Use of a resistor between pin 5 and 7 will decrease gain and delay time.
Common mode transient immunity in logic high level is the maximum tolerable (positive) dv
CM
/ dt on
the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a logic high
state (i.e., V
O
> 2.0V).
Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dv
CM
/ dt on
the trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic
low state (i.e., V
O
< 0.8V).
4
2007-10-01
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
