100398
Logic Symbol
Pin Descriptions
Pin Names
E
0
–E
3
E
0
–E
3
T
0
–T
3
OE
Description
ECL Data I/O
Complementary ECL
Data I/O
TTL Data I/O
Output Enable Input Levels
Latch Enable Input Levels
Direction Control
Input (TTL levels)
GNDECL
GNDECLO
GNDS
V
EE
V
EED
GNDTTL
GNDTTLD
V
TTL
V
TTLD
ECL Ground
ECL Output Ground
ECL Ground-to-Substrate
ECL Quiescent Power Supply
ECL Dynamic Power Supply
TTL Quiescent Ground
TTL Dynamic Ground
TTL Quiescent Power Supply
TTL Dynamic Power Supply
Connection Diagrams
24-Pin DIP
LE
DIR
Truth Table
28-Pin PLCC
LE
0
0
0
0
1
1
1
1
DIR
0
0
1
1
0
0
1
1
OE
0
1
0
1
0
1
0
1
ECL
Port
LOW
(Cut-Off)
Input
LOW
(Cut-Off)
Output
Input
Latched
Low
(Cut-Off)
Latched
X
(Note 2)(Note 3)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don’t Care
Z
=
High Impedance
Note 1:
ECL input to TTL output mode.
Note 2:
TTL input to ECL output mode.
Note 3:
Retains data present before LE set HIGH.
Note 4:
Latch is transparent.
TTL
Port
Z
Notes
Output (Note 1)(Note 4)
Z
Input
Z
X
Input
(Note 2)(Note 4)
(Note 1)(Note 3)
(Note 1)(Note 3)
(Note 2)(Note 3)
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