100390
Application Notes
1. Device performance will be enhanced by the use of
dual V
CC
power planes as illustrated in the Application
Figures 4, 5. This will minimize the coupling of TTL
switching noise into the primary reference to the ECL
circuitry and take full advantage of the 100390’s on
chip V
CC
partitioning.
2. The device’s partitioned V
CC
may be operated from two
5V, 5% tolerance, supplies provided that they are
ramped up/down together so that the max differential is
1V. This is to prevent overstress to internal ESD
diodes. If the ECL driver to the F390 is powered from a
separate supply, it must obey this sequence rule also.
3. Glitch-free power up, independent of Data input levels,
is achieved if TTL logic HIGH is held on the Output
Enable pin during ramping up/down of the V
CC
supply.
4. Undefined output states can occur for some invalid
combinations. See Truth Table. This should be avoided
to prevent possible oscillation or increased power con-
sumption due to TTL outputs biased into a quasi state
with both pullup and pulldown stages partially on.
3-STATEing the outputs will counteract the effects of
invalid input states.
5. Pins 8, 15, and 22 on the 28-pin PLCC package are
tied to the chip’s substrate and are named GNDs.
These pins are electrically common to the ground pins
1, 2, and 28. For best thermal performance, tie the
GND pins to the circuit ground plane. They may be tied
to an electrically isolated thermal dissipation plane or
may float.
6. Figure 4 illustrates typical differential input operation.
7. Figure 5 illustrates typical single-ended input operation.
FIGURE 4.
FIGURE 5.
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