E S I
E S I
ADVANCED INFORMATION
Excel Semiconductor inc.
During the unlock-bypass mode, only the unlock-
bypass program and unlock-bypass reset com-
mands are valid. To exit the unlock-bypass mode,
the system must issue the two-cycle unlock-bypass
reset command sequence. The first cycle must con-
tain the bank address and the data 90h. The sec-
ond cycle need to only contain the data 00h. The
bank then returns to the read mode.
Table 9 shows the address and data requirements for
the chip erase command sequence. Note that the
autoselect, security sector, and CFI modes are
unavailable while an erase operation is in progress.
Erase Status Bits : DQ7, DQ6, DQ2, or RY/BY#
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section Table 10 for information on these status bits.
- Unlock Bypass Enter Command
- Unlock Bypass Reset Command
- Unlock Bypass Program Command
Unlock Bypass Program during WP#/ACC
Accelerated Program Mode
Commands Ignored during Erase Operation
The device offers accelerated program operations
through the WP#/ACC pin. When the system
Any command written during the chip erase opera-
tion are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that
occurs, the chip erase command sequence should
be reinitiated once that bank has returned to reading
array data to ensure data integrity. Fig. 9 illustrates
the algorithm for the erase operation. Refer to the
Erase and Program Operations tables in the AC
Characteristics section for parameters, and Fig. 23
section for timing diagrams.
asserts V on the WP#/ACC pin, the device auto-
HH
matically enters the unlock bypass mode. The sys-
tem may then write the two-cycle unlock bypass
program command sequence. The device uses the
higher voltage on the WP#/ACC pin to accelerate
the operation. Note that the WP#/ACC pin must not
be at V
in any operation other than accelerated
HH
programming, or device damage may result. In
addition, the WP#/ACC pin must not be left floating
or unconnected; inconsistent behavior of the device
may result. Fig. 8 illustrates the algorithm for the
program operation. Refer to the Erase and Program
Operations table in the AC Characteristics section
for parameters, and Fig. 22 for timing diagrams.
SECTOR ERASE COMMAND
By using a sector erase command, a single sector or
multiple sectors can be erased. The sector erase
command is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 9 shows the
address and data requirements for the sector erase
command sequence. Note that the autoselect, secu-
rity sector, and CFI modes are unavailable while an
erase operation is in progress.
CHIP ERASE COMMAND
To erase the entire memory, a chip erase command
is used. This command is a six bus cycle operation.
The chip erase command sequence is initiated by
writing two unlock cycles, followed by a set-up com-
mand. Two additional unlock write cycles are then
followed by the chip erase command, which in turn
invokes the Embedded Erase algorithm. The chip
erase command erases the entire memory includ-
ing all other sectors except the protected sectors,
but the internal erase operation is performed on a
single sector base.
Embedded Sector Erase Algorithm
The device does not require the system to prepro-
gram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire mem-
ory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings these operations.
Embedded Erase Algorithm
The device does not require the system to prepro-
gram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the
entire memory for an all zero data pattern prior to
electrical erase. The system is not required to pro-
vide any controls or timings during these opera-
tions.
26
Rev. 0E May 25, 2006
ES29DL320
EXCELSEMI [ EXCEL SEMICONDUCTOR INC. ]
