欢迎访问ic37.com |
会员登录 免费注册
发布采购

EID1415A1-3 参数 Datasheet PDF下载

EID1415A1-3图片预览
型号: EID1415A1-3
PDF下载: 下载PDF文件 查看货源
内容描述: 14.40-15.35GHz , 3瓦的内部匹配功率FET [14.40-15.35GHz, 3-Watt Internally-Matched Power FET]
分类和应用:
文件页数/大小: 2 页 / 131 K
品牌: EXCELICS [ EXCELICS SEMICONDUCTOR, INC. ]
 浏览型号EID1415A1-3的Datasheet PDF文件第2页  
EID1415A1-3
ISSUED: 02/19/2009
14.40-15.35GHz, 3-Watt Internally-Matched Power FET
Excelics
EID1415A1-3
FEATURES
14.40-15.35GHz Bandwidth
Input/Output Impedance Matched to 50 Ohms
+34.5 dBm Output Power at 1dB Compression
8.0 dB Power Gain at 1dB Compression
30% Power Added Efficiency
Hermetic Metal Flange Package
YM
SN
ELECTRICAL CHARACTERISTICS (T
a
= 25°C)
SYMBOL
P
1dB
G
1dB
∆G
PAE
Id
1dB
I
DSS
V
P
R
TH
PARAMETERS/TEST CONDITIONS
1
Output Power at 1dB Compression f = 14.40-15.35GHz
V
DS
= 10 V, I
DSQ
700 mA
Gain at 1dB Compression
f = 14.40-15.35GHz
V
DS
= 10 V, I
DSQ
700 mA
Gain Flatness
f = 14.40-15.35GHz
V
DS
= 10 V, I
DSQ
700 mA
Power Added Efficiency at 1dB Compression
V
DS
= 10 V, I
DSQ
700 mA
f = 14.40-15.35GHz
Drain Current at 1dB Compression f = 14.40-15.35GHz
Saturated Drain Current
Pinch-off Voltage
Thermal Resistance
3
2. S.C.L. = Single Carrier Level.
3. Overall Rth depends on case mounting.
Caution! ESD sensitive device.
MIN
33.5
7.0
TYP
34.5
8.0
+ 0.6
30
750
1040
-1.2
11.0
900
1440
-2.5
12.0
o
MAX
UNITS
dBm
dB
dB
%
mA
mA
V
C/W
V
DS
= 3 V, V
GS
= 0 V
V
DS
= 3 V, I
DS
= 10 mA
Notes:
1. Tested with 100 Ohm gate resistor.
ABSOLUTE MAXIMUM RATINGS FOR CONTINUOUS OPERATION
1,2
SYMBOL
V
DS
V
GS
I
DS
I
GSF
P
IN
P
T
T
CH
T
STG
CHARACTERISTIC
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Forward Gate Current
Input Power
Total Power Dissipation
Channel Temperature
Storage Temperature
VALUE
10 V
-3 V
IDSS
20 mA
@ 3dB compression
10 W
150°C
-65/+150°C
Notes:
1.
Operating the device beyond any of the above ratings may result in permanent damage or reduction of MTTF.
2.
Bias conditions must also satisfy the following equation P
T
< (T
CH
–T
PKG
)/R
TH
; where T
PKG
= temperature of package,
and P
T
= (V
DS
* I
DS
) – (P
OUT
– P
IN
).
Specifications are subject to change without notice.
Excelics Semiconductor, Inc. 310 De Guigne Drive, Sunnyvale, CA 94085
Phone: 408-737-1711 Fax: 408-737-1868 Web:
www.excelics.com
page 1 of 2
Revised February 2009