EIC1415-3
UPDATED 11/22/2004
14.40 – 15.35GHz 3-Watt Internally Matched Power FET
.060 MIN.
FEATURES
•
•
•
•
•
•
•
•
14.40-15.35 GHz Bandwidth
Input/Output Impedance Matched to 50 Ohms
+34.5 dBm Output Power at 1dB Compression
6.0 dB Power Gain at 1dB Compression
25% Power Added Efficiency
-42 dBc IM3 at Po = 23.5 dBm SCL
Hermetic Metal Flange Package
100% Tested for DC, RF, and R
TH
Excelics
EIC1415-3
GATE
DRAIN
.060 MIN.
.650±.008 .512
.319
.022
YM
SN
.094
.382
.045
.004
.070 ±.008
.129
ALL DIMENSIONS IN INCHES
ELECTRICAL CHARACTERISTICS (T
a
= 25°C)
SYMBOL
P
1dB
G
1dB
∆G
PAE
Id
1dB
IM3
Caution! ESD sensitive device.
MIN
33.5
5.0
TYP
34.5
6.0
±0.6
25
900
-38
-42*
1400
-2.5
8.0
1800
-4.0
9.0
o
PARAMETERS/TEST CONDITIONS
1
Output Power at 1dB Compression f = 14.40-15.35GHz
V
DS
= 10 V, I
DSQ
≈
800mA
Gain at 1dB Compression
f = 14.40-15.35GHz
V
DS
= 10 V, I
DSQ
≈
800mA
Gain Flatness
f = 14.40-15.35GHz
V
DS
= 10 V, I
DSQ
≈
800mA
Power Added Efficiency at 1dB Compression
V
DS
= 10 V, I
DSQ
≈
800mA
f = 14.40-15.35GHz
Drain Current at 1dB Compression f = 14.40-15.35GHz
Output 3rd Order Intermodulation Distortion
2
∆f
= 10 MHz 2-Tone Test; Pout = 23.5 dBm S.C.L
V
DS
= 10 V, I
DSQ
≈
65% IDSS
f = 15.35GHz
MAX
UNITS
dBm
dB
dB
%
1100
mA
dBc
mA
V
C/W
I
DSS
V
P
R
TH
Notes:
1.
*
Saturated Drain Current
Pinch-off Voltage
Thermal Resistance
3
V
DS
= 3 V, V
GS
= 0 V
V
DS
= 3 V, I
DS
= 15 mA
Tested with 100 Ohm gate resistor.
2.
S.C.L. = Single Carrier Level.
3.
Overall Rth depends on case mounting.
These devices are available screened for IM3 performance. Please contact factory with your requirement.
ABSOLUTE MAXIMUM RATINGS FOR CONTINUOUS OPERATION
1,2
SYMBOL
V
DS
V
GS
I
DS
I
GSF
P
IN
P
T
T
CH
T
STG
CHARACTERISTIC
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Forward Gate Current
Input Power
Total Power Dissipation
Channel Temperature
Storage Temperature
VALUE
10 V
-4.5 V
IDSS
30 mA
@ 3dB compression
14 W
150°C
-65/+150°C
Notes:
1.
Operating the device beyond any of the above ratings may result in permanent damage or reduction of MTTF.
2.
Bias conditions must also satisfy the following equation P
T
< (T
CH
–T
PKG
)/R
TH
; where T
PKG
= temperature of package, and P
T
= (V
DS
* I
DS
) – (P
OUT
– P
IN
).
Specifications are subject to change without notice.
Excelics Semiconductor, Inc. 310 De Guigne Drive, Sunnyvale, CA 94085
page 1 of 1
Phone: 408-737-1711 Fax: 408-737-1868 Web:
www.excelics.com
Revised December 2004
EXCELICS [ EXCELICS SEMICONDUCTOR, INC. ]
