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EFE960BVR-5759 参数 Datasheet PDF下载

EFE960BVR-5759图片预览
型号: EFE960BVR-5759
PDF下载: 下载PDF文件 查看货源
内容描述: 5.70-5.90GHz 4瓦部分匹配功率场效应管 [5.70-5.90GHz 4-Watt Partially Matched Power FET]
分类和应用:
文件页数/大小: 3 页 / 122 K
品牌: EXCELICS [ EXCELICS SEMICONDUCTOR, INC. ]
 浏览型号EFE960BVR-5759的Datasheet PDF文件第2页浏览型号EFE960BVR-5759的Datasheet PDF文件第3页  
EFE960BVR-5759
UPDATED 10/26/2006
5.70-5.90GHz 4-Watt Partially Matched Power FET
FEATURES
5.70-5.90 GHz Bandwidth
+36.0 dBm Output Power at 1dB Compression
9.0 dB Power Gain at 1dB Compression
25% Power Added Efficiency
-46 dBc IM3 at Po = 24.5 dBm SCL
Non-Hermetic 180 Mil Metal Flange Package
100% Tested for DC, RF, and R
TH
ELECTRICAL
CHARACTERISTICS (T
a
= 25°C)
SYMBOL
P
1dB
G
1dB
PAE
Id
1dB
IM3
I
DSS
V
P
R
TH
Notes:
Caution! ESD sensitive device.
MIN
35.0
8.0
PARAMETERS/TEST CONDITIONS
1
Output Power at 1dB Compression
V
DS
= 10 V, I
DSQ
1100mA
Gain at 1dB Compression
V
DS
= 10 V, I
DSQ
1100mA
f = 5.8GHz
f = 5.8GHz
TYP
36.0
9.0
25
1300
MAX
UNITS
dBm
dB
%
Power Added Efficiency at 1dB Compression
V
DS
= 10 V, I
DSQ
1100mA
f = 5.8GHz
Drain Current at 1dB Compression
f = 5.8GHz
Output 3rd Order Intermodulation Distortion
2
∆f
= 10 MHz 2-Tone Test; Pout = 24.5 dBm S.C.L
V
DS
= 10 V, I
DSQ
65% IDSS
f = 5.8GHz
Saturated Drain Current
Pinch-off Voltage
Thermal Resistance
3
1400
mA
dBc
-43
-46
2000
-2.5
5.5
2500
-4.0
6.0
V
DS
= 3 V, V
GS
= 0 V
V
DS
= 3 V, I
DS
= 20 mA
mA
V
o
C/W
1. FET TO BE TESTED IN EXCELICS EVALUATION BOARD.
2. S.C.L. = Single Carrier Level.
3. OVERALL Rth DEPENDS ON CASE MOUNTING.
DATA REFERS TO EDGES OF PACKAGE.
MAXIMUM RATINGS AT 25
O
C
SYMBOLS
V
DS
V
GS
Igf
Igr
Pin
Tch
Tstg
Pt
PARAMETERS
Drain-Source Voltage
Gate-Source Voltage
Forward Gate Current
Reversed Gate Current
Input Power
Channel Temperature
Storage Temperature
Total Power Dissipation
ABSOLUTE
1
15V
-5V
43.2 mA
-7.2 mA
33 dBm
175 C
o
-65/175 C
o
CONTINUOUS
2
10V
-4.5V
14.4 mA
-2.4 mA
@ 3dB Compression
175
o
C
-65/175
o
C
25W
25W
Notes:
1.
Operating the device beyond any of the above ratings may result in permanent damage or reduction of MTTF.
2.
Bias conditions must also satisfy the following equation P
T
< (T
CH
–T
PKG
)/R
TH
; where T
PKG
= temperature of package, and
P
T
= (V
DS
* I
DS
) – (P
OUT
– P
IN
).
Specifications are subject to change without notice.
Excelics Semiconductor, Inc. 310 De Guigne Drive, Sunnyvale, CA 94085
page 1 of 3
Phone: 408-737-1711 Fax: 408-737-1868 Web:
www.excelics.com
Revised November 2006