欢迎访问ic37.com |
会员登录 免费注册
发布采购

XRT83SL28IV 参数 Datasheet PDF下载

XRT83SL28IV图片预览
型号: XRT83SL28IV
PDF下载: 下载PDF文件 查看货源
内容描述: 8路E1短程线路接口单元 [8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT]
分类和应用: 数字传输接口电信集成电路电信电路PC
文件页数/大小: 47 页 / 1000 K
品牌: EXAR [ EXAR CORPORATION ]
 浏览型号XRT83SL28IV的Datasheet PDF文件第30页浏览型号XRT83SL28IV的Datasheet PDF文件第31页浏览型号XRT83SL28IV的Datasheet PDF文件第32页浏览型号XRT83SL28IV的Datasheet PDF文件第33页浏览型号XRT83SL28IV的Datasheet PDF文件第35页浏览型号XRT83SL28IV的Datasheet PDF文件第36页浏览型号XRT83SL28IV的Datasheet PDF文件第37页浏览型号XRT83SL28IV的Datasheet PDF文件第38页  
XRT83SL28  
xr  
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT  
REV. 1.0.0  
4.2  
16-Bit Serial Data Input Description  
The serial data input is sampled on the rising edge of SCLK. In read-back mode, the serial data output is  
updated on the falling edge of SCLK. The serial data must be applied to the LIU LSB first. The 16 bits of serial  
data are described below.  
4.2.1  
R/W (SCLK1)  
The first serial bit applied to the LIU informs the microprocessor that a Read or Write operation is desired. If the  
R/W bit is set to “0”, the microprocessor is configured for a Write operation. If the R/W bit is set to “1”, the  
microprocessor is configured for a Read operation.  
4.2.2  
A[5:0] (SCLK2 - SCLK7)  
The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0  
(LSB) must be sent to the LIU first followed by A1 and so forth until all 6 address bits have been sampled by  
SCLK.  
4.2.3  
X (Dummy Bit SCLK8)  
The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data  
if the read-back mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold  
either “0” or “1” during both Read and Write operations.  
4.2.4  
D[7:0] (SCLK9 - SCLK16)  
The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the  
address bits. D0 (LSB) must be sent to the LIU first followed by D1 and so forth until all 8 data bits have been  
sampled by SCLK. Once 16 SCLK cycles have been complete, the LIU holds the data until CS is pulled “High”  
whereby, the serial microprocessor latches the data into the selected internal register.  
4.3  
8-Bit Serial Data Output Description  
The serial data output is updated on the falling edge of SCLK9 - SCLK16 if R/W is set to “1”. D0 (LSB) is  
provided on SCLK9 to the SDO pin first followed by D1 and so forth until all 8 data bits have been updated. The  
SDO pin allows the user to read the contents stored in individual registers by providing the desired address on  
the SDI pin during the Read cycle.  
32  
 复制成功!